Durga Prasad Sahoo

Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA

Physically Unclonable Function (PUF) designs proposed in the recent literature vary widely in diverse characteristics such as hardware resource requirement, reliability, entropy, and robustness against mathematical cloning. Most of the standalone PUF designs suffer from either poor performance profile or unacceptable resource-overhead. We present a novel PUF design paradigm, termed as PUF Composition, that utilizes smaller PUFs as design building blocks to define a “Composite PUF” having larger challenge-space and superior performance profile at reasonable resource-overhead. A formal framework for PUF composition based on a probabilistic model has also been developed to enable the Composite PUF designer to have a-priori estimate of the relative qualities of several composite PUF options, without actually implementing them physically. The notion of PUF composition, and the probabilistic model developed for delay-PUFs, have both been validated using Ring Oscillator PUF (ROPUF) and Arbiter PUF (APUF) on Xilinx Spartan-3 Field Programmable Gate Array (FPGA).

Design of low area-overhead ring oscillator PUF with large challenge space

Exorbitantly high resource-overhead is an important limiting factor for designing a Ring Oscillator Physically Unclonable Function (ROPUF) with large challenge-space. This work presents a design approach for large ROPUF with much lesser resource than that required for classical ROPUF design. It exploits small ROPUFs as design building blocks. Quality of the proposed scheme has been validated by the design of 60-bit ROPUF on Altera FPGA (Field Programmable Gate Array) that is physically infeasible according to previously proposed direct design principles. The hardware resource required for the 60-bit proposed ROPUF design is lesser than that for 10-bit classic ROPUF. In addition, implementation of 60-bit proposed ROPUF shows 47% uniqueness and 91 % reliability on average.

A Novel Memristor-Based Hardware Security Primitive

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learning-based modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

A novel memristor based physically unclonable function

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this paper, we first introduce a novel hybrid memristor-CMOS XOR/XNOR logic circuit that offers several advantages such as combinational circuit behavior, simpler operation and lower hardware overhead than existing solutions. Then, we use this XOR circuit as a component to design a hybrid memristor-CMOS PUF circuit and demonstrate its effectiveness through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially lesser hardware overhead than previously proposed memristor-based PUF circuits, while being resistant against machine learning based modelling attacks. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security. HighlightsWe propose a novel hybrid memristor-CMOS XOR/XOR gate.It has pure combinational behavior.Novel hybrid memristor-CMOS PUF circuit.Low VLSI design overhead.Resistant against modelling attacks.

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In the existing literature on PUFs, the Hamming Distance Test, denoted by HDT(t), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC(t). The objective of these test schemes is to estimate the output transition probability when there are t or fewer than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test, which is denoted as HDT(e, t). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t. As a contribution, we provide a comprehensive discussion and analytic interpretation of HDT(t), PC(t), and HDT(e, t) test schemes for Arbiter PUF (APUF), Exclusive-OR (XOR) PUF, and Lightweight Secure PUF (LSPUF). Our analysis establishes that HDT(e, t) test is more general in comparison with HDT(t) and PC(t) tests. In addition, we demonstrate a few scenarios where the adversary can exploit the information obtained from the analysis of HDT(e, t) properties of APUF, XOR PUF, and LSPUF to develop statistical attacks on them, if the ideal value of HDT(e, t) = 0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and Field Programmable Gate Array (FPGA) implemented APUF, XOR PUF, and LSPUF designs.

Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective

Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias-free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA-based APUF implementation is the Programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal APUF on Xilinx FPGA using the standard Xilinx CAD tool flow. The main insight is to exploit the Hard Macro feature of the Xilinx design flow to design bias-free symmetric delay paths. We have demonstrated the effectiveness and superiority of our design to previously proposed PDL-based PUFs through implementation and characterization results.

Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set

Physically Unclonable Function (PUF) circuits are an important class of hardware security primitives that promise a paradigm shift in applied cryptography. Ring Oscillator PUF (ROPUF) is an important PUF variant, but it suffers from hardware overhead limitations, which in turn restricts the size of its challenge space. To overcome this fundamental shortcoming, improved ROPUF variants based on the subset selection concept have been proposed, which significantly “expand” the challenge space of a ROPUF at acceptable hardware overhead. In this paper, we develop cryptanalytic attacks on a previously proposed low-overhead and robust ROPUF variant. The proposed attacks are practical as they have quadratic time and data complexities in the worst case. We demonstrate the effectiveness of the proposed attack by successfully attacking a public domain dataset acquired from FPGA implementations.

Cryptanalysis of Composite PUFs (Extended abstract-invited talk)

In recent years, Physcially Unclonable Functions (PUFs) have become important cryptographic primitive and are used in secure systems to resist physical attacks. Since PUFs have many useful properties such as memory-leakage resilience, unclonablity, tampering-resistance, PUF has drawn great interest in academia as well as industry. As extremely useful hardware security primitives, PUFs are used in various proposed applications such as device authentication and identification, random number generation, and intellectual property protection. One of important requirement to PUFs is that PUFs should have small hardware overhead in order to be utilized in lightweight application such as RFID. To achieve this goal, Composite PUFs are developed and introduced in RECONFIG2013 and HOST2014. In a nutshell, Composite PUFs are built by using many small PUFs primitives. In this talk, we show that Composite PUFs introduced in RECONFIG2013 are not secure by presenting its cryptanalysis.

A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security

Arbiter Physically Unclonable Functions (APUFs), while being relatively lightweight, are extremely vulnerable to modeling attacks. Hence, various compositions of APUFs such as XOR APUF and Lightweight Secure PUF have been proposed to be secure alternatives. Previous research has demonstrated that PUF compositions have two major challenges to overcome: vulnerability against modeling and statistical attacks, and lack of reliability. In this paper, we introduce a multiplexer-based composition of APUFs, denoted as MPUF, to simultaneously overcome these challenges. In addition to the basic MPUF design, we propose two MPUF variants namely cMPUF and rMPUF to improve the robustness against cryptanalysis and reliability-based modeling attack, respectively. An rMPUF demonstrates enhanced robustness against the reliability-based modeling attack, while even the well-known XOR APUF, otherwise robust to machine learning based modeling attacks, has been modeled using the same technique with linear data and time complexities. The rMPUF can provide a good trade-off between security and hardware overhead while maintaining a significantly higher reliability level than any practical XOR APUF instance. Moreover, MPUF variants are the first APUF compositions, to the best of our knowledge, that can achieve Strict Avalanche Criterion without using any additional input network (or hardware) for challenge transformation. Finally, we validate our theoretical findings using Matlab-based simulations of MPUFs.

Automated Design of High Performance Integer Arithmetic Cores on FPGA

We present the principles of operation and functioning of a CAD software tool for the automated realization of high performance integer arithmetic circuits targeting Xilinx Field Programmable Gate Arrays (FPGAs). The key ideas behind the improvement of circuit performance are optimal usage of the hardware primitives available on the Xilinx FPGA platform, as well as regular, careful and constrained placement of the circuit building blocks on the FPGA fabric. The bit - sliced architectures of our proposed designs allow us to automatically generate synthesizable, platform - specific structural Hardware Description Language (HDL) code for the proposed circuits, as well as the placement constraint files needed to control the placement of the design on the given FPGA fabric. Compared against circuits implemented using existing approaches and those automatically generated using existing CAD tools, our automatically generated implementations demonstrate significant speed improvement.