Sebastian Hoyos

Mixed-signal parallel compressed sensing and reception for cognitive radio

A parallel structure to do spectrum sensing in cognitive radio (CR) at sub-Nyquist rate is proposed. The structure is based on compressed sensing (CS) that exploits the sparsity of frequency utilization. Specifically, the received analog signal is segmented or time-windowed and CS is applied to each segment independently using an analog implementation of the inner product, then all the samples are processed together to reconstruct the signal. Applying the CS framework to the analog signal directly relaxes the requirements in wideband RF receiver front-ends. Moreover, the parallel structure provides a design flexibility and scalability on the sensing rate and system complexity. This paper also provides a joint reconstruction algorithm that optimally detects the information symbols from the sub-Nyquist analog projection coefficients. Simulations showing the efficiency of the proposed approach are also presented.

Monobit digital receivers for ultrawideband communications

Ultrawideband systems employ short low-power pulses. Analog receiver designs can accommodate the required bandwidths, but they come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital converter (ADC) resolution and power consumption. In this paper, we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: 1) fixed reference; 2) stochastic reference; and 3) sigma-delta modulation (SDM). These are compared for two types of receivers based on: 1) matched filtering; and 2) transmitted reference. Bit-error rate (BER) expressions are developed for these systems and compared to full-resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full-resolution digital receiver.

A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing

This paper presents a sub-Nyquist rate sampling receiver architecture that exploits signal sparsity by employing compressive sensing (CS) techniques. The receiver serves as an analog-to-information conversion system that works at sampling rates much lower than the Nyquist rate. A parallel-path structure that employs current mode sampling techniques is used. The receiver performance is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with a 90-nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that an instantaneous receiver signal bandwidth of 1.5 GHz and a signal-to-noise-plus-distortion ratio of 44 dB are achievable. The receiver power consumption is estimated to be 120.8 mW. A comparison with state-of-the-art high-speed analog-to-digital conversions reveals that the proposed approach improves the figure of merit by a factor of three if the signal exhibits a 4% sparsity.

Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization

This paper presents a wideband common-gate (CG) LNA architecture that overcomes the fundamental tradeoff between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure (NF) over the previously reported feedback amplifiers in a CG configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. An amplifier prototype was realized in 0.18-μm CMOS, operates from 1.05 to 3.05 GHz, and dissipates 12.6 mW from 1.8-V supply while occupying a 0.073-mm2 active area. The LNA provides 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than - 10-dB input matching, and - 0.7-dBm minimum IIP3 across the entire bandwidth.

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.

A 2.8-mW Sub-2-dB Noise-Figure Inductorless Wideband CMOS LNA Employing Multiple Feedback

A wideband low-noise amplifier (LNA), which is a key block in the design of broadband receivers for multiband wireless communication standards, is presented in this paper. The LNA is a fully differential common-gate structure. It uses multiple feedback paths, which add degrees of freedom in the choice of the LNA transconductance to reduce the noise figure (NF) and increase the amplification. The proposed LNA avoids the use of bulky inductors that leads to area and cost saving. A prototype is implemented in IBM 90-nm CMOS technology. It covers the frequency range of 100 MHz to 1.77 GHz. The core consumes 2.8 mW from a 2-V supply occupying an area of 0.03 mm2. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB, while the average NF is 2 dB across the whole band. The LNA achieves a return loss greater than 10 dB across the entire band and a third-order input intercept point IIP3 of - 2.85 dBm at the maximum gain frequency.

A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth

This paper presents a sixth-order bandpass ΣΔ modulator with 10 MHz bandwidth and 200 MHz center frequency suitable for high-IF applications. The fs/4 modulator employs an 800 MHz clock frequency and uses an active RC loop filter implemented with three-stage linearized operational amplifiers achieving more than 50 dB gain at 200 MHz. Furthermore, a calibration technique is proposed to compensate for process-voltage-temperature (PVT) variations, which involves measurement and optimization of the noise transfer function by injecting two auxiliary tones at the quantizer input. The modulator achieves 68.4 dB peak SNDR measured in 10 MHz bandwidth and IM3 of -73.5 dB at -2 dBr input signal. Fabricated in a vanilla 0.18 μm CMOS technology, the modulator consumes 160 mW (static + dynamic power) and occupies an active silicon area of 2.5 mm2.

Background ADC calibration in digital domain

A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.

Broadband multicarrier communication receiver based on analog to digital conversion in the frequency domain

This paper introduces a multicarrier communication receiver for broadband applications based on analog to digital conversion (ADC) of the received signal in the frequency domain. The samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since It efficiently parallelizes the A/D conversion reducing the sampling speed requirements. We show that the sampling rate requirements are relaxed as the number of frequency samples is increased, which introduces a trade-off between complexity and sampling rate. The new receiver possesses additional advantages, including scalability with increasing frequency samples, the possibility of optimally allocating the available number of bits for the ATD conversion across the frequency domain samples which potentially reduces the distortion introduced by the high-speed ADC, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers. We also investigate how the proposed receiver responds to common multicarrier communication receiver problems such as phase noise and channel frequency selectivity.

Compressed UWB signal detection with narrowband interference mitigation

Operating at sub-Nyquist rate, compressed sensing (CS) has been successfully applied to the design of impulse ultra-wideband (I-UWB) receivers where Nyquist sampling is a formidable challenge. However, strong narrowband interference (NBI) can easily jam and saturate the receiver front-end and greatly degrade the system performance. In this paper, CS is applied to the design of I-UWB receivers with NBI mitigation. By exploiting the sparsity of the NBI within the pulse UWB spectrum, a compressive measurement matrix can be designed that is not only efficient at collecting signal energy, but also nulls out the NBI effectively. The performance analysis of the proposed receiver is provided. Simulation results show the effectiveness of the proposed method for UWB signal detection and NBI mitigation.