Ehsan Zhian Tabasy

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing ( 2Vpp and 4Vpp) drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the 4Vpp transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 μW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves -9 dBm sensitivity at a BER=10-9 and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 μApp sensitivity at 10 Gb/s and more than 40% power reduction with higher input current levels.

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver

Silicon photonic links based on ring-resonator devices provide a unique opportunity to deliver distance-independent connectivity, whose pin-bandwidth scales with the degree of wavelength-division multiplexing. However, reliability and robustness are major challenges to widespread adoption of ring-based silicon photonics. In this work, a CMOS photonic transceiver architecture is demonstrated that incorporates the following enhancements: transmitters with independent dual-edge pre-emphasis to compensate for modulator bandwidth limitations; a bias-based tuning loop to calibrate for resonance wavelength variations; and an adaptive sensitivity-bandwidth receiver that can self-adapt for insitu variations in input capacitance, modulator/photodetector performance, and link budget.

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications

High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm 2 area.

Embedded equalization for ADC-based serial I/O receivers

In this paper, the performance impact of embedding partial equalization in ADC-based receivers is analyzed. A hybrid ADC receiver architecture which includes embedded equalization and selective digital equalization power-down based on threshold detection is proposed.

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies 0.81 mm2 area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW.

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS

A 25GS/s 8-way time-interleaved binary search ADC employs a novel soft-decision selection algorithm to improve metastability tolerance and relax T/H settling requirements. The T/H design is further relaxed with reduced loading from a new shared-input three comparator structure. Fabricated in GP 65nm CMOS, the ADC achieves 4.62-bits ENOB at Nyquist and 143 fJ/conv.-step FOM, while consuming 88mW and occupying 0.24mm2 core ADC area.

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS

ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer.

Statistical modeling of metastability in ADC-based serial I/O receivers

This paper develops metastability error models for flash and asynchronous SAR ADCs and describes a novel ADC-based receiver statistical modeling methodology to analyze the BER performance impact of metastability error propagation through digital FFE equalization.

Sequential Correlated Level Shifting: A Switched-Capacitor Approach for High-Accuracy Systems

Analog circuit accuracy is severely limited by finite and nonlinear opamp gain. For switched-capacitor circuits, correlated level shifting (CLS) is an effective technique to improve system accuracy with negligible additive noise. A modification of this method, called sequential CLS, is introduced in this brief, which provides dramatic increases in the effective accuracy of a switched-capacitor structure. Measurements of prototype sample-and-hold structures utilizing simple single-stage opamps in an LP 90-nm CMOS technology show that at the same power and area consumption, the proposed modification can improve the settling accuracy of simple CLS from 5.8 to 8.8 bits with two additional sequential steps.