Azami Zaharim

Practical framework of employability skills for engineering graduate in Malaysia

The purpose of this paper is to propose a practical and simple framework of engineering employability skills that will allow the concept to be explained easily and that can be used as a framework for working with engineering graduates to develop their employability before entering workforce. The framework was developed from existing researches on engineering employability skills issues and the requirement of the accreditation of engineering programme. The various skills of employability skills related to engineering included in the framework are discussed and their criteria justified bases on literature review of existing studies. The framework sets out exactly what is meant by engineering employability, in clear and simple terms, and the framework suggests directions for interaction between the various skills. The relationships between the skills within the framework remain theoretical. Further research to test the framework is planned and will be reported in future paper. The framework can be used to explain the concept of employability to those new to the subject, and particularly to engineering students and their future employer. It will be a useful tool for lecturers, careers advisors, trainers, employers and any other practitioners involved in employability skills. It will also be used to develop a model and a measurement tool for engineering employability skills. This paper contributes insights into the linking of graduate attributes, using national accreditation criteria and the framework of engineering employability skills from locally and globally expectation. It will be of value to anybody with an interest in employability issues.

Employability skills for an entry-level engineer as seen by Malaysian employers

In an earlier publication, the authors have proposed a model on practical framework of engineering employability skills, i.e. the Malaysian Engineering Employability Skills (MEES). The framework discusses on the possible employability skills as required for an entry level engineer in Malaysia based on many other earlier studies. A set of questionnaires was later developed to gauge this model from the perspective of Malaysian employers from engineering sectors. Based on the results obtained, this paper will discuss, among others, the preferred entry-level employability skills as valued by employers when hiring fresh engineering graduates. The data was collected from September to December 2009 through face-to-face and telephone interviews with employers from Kelang Valley area, the main industrial area in Malaysia. Five hundreds employers were approached, and of this, three hundreds were successfully interviewed. The interviews were only carried out with high ranking officers, in this case; Head of Division or higher to assure accurate results. The questionnaires comprise ten (10) main employability skills as described in MEES. A “multi-attribute value technique” and statistical methods were used for data analysis. The findings suggested that the employers perceived employability skills as “required” with an average rating score of 4.06 out of 5.00. The most required skill is “communication skills” while the least required is “engineering system approach”. However, there are differences in the priorities of employability skills by the four different categories of industries considered in this study. The framework and the findings presented perhaps can be used as guidance for the employers in their recruitment exercise. The findings could also be helpful in guiding the education providers, trainers, career advisors and the likes in increasing the employability skills of engineering fresh graduates.

Forecasting of ionospheric delay over Parit Raja Station, Johor, using statistical method

GPS is of great importance in precise positioning, however, the accuracy is marked by error sources, i.e. ionospheric effects. The signal information is delayed and the carrier phase experiences an advance due to the dispersive character of the ionosphere. The delay can be more than 100 meters in the worst case scenario and tends to increase with increasing solar activity. This error can be corrected by processing the GPS data if it is known. This paper describes the possibility of using statistical methods to forecast the ionospheric delay which shows repeatable patterns in time series. The statistical method used is the Holt-Winter method due to its ability to forecast time series with repeated trends and seasonal patterns. Based on the TEC data collected during a period of a month, ionospheric delay forecast is generated for the following month, which is then compared with the real data. Results show that there is a 6% error between the forecast and the real ionospheric delay and the error correction for the delay can be more than 90%.

Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLASs simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to −0.1501V and +0.150047V respectively.

Cobalt silicide and titanium silicide effects on nano devices

This paper describes growth process of the two silicide Sub-nanometer devices and the different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS devices. On the top of CMOS device gate, metal silicide is developed on-top of the polysilicon to produce an ohmic contact between the polysilicon and aluminum wire. The ohmic contact should be better compared to metal-polysilicon borders. This silicide has been widely used to reduce resistance of polysilicon gates. Metal silicides such as titanium silicide (TiSi2), tungsten salicide (WSi2), cobalt salicide (CoSi2) andnickel salicide (NiSi2) are widely used for this purpose. These metals react with polysilicon, to form metal silicide layer that possesses better physical and electrical properties to interface with aluminium. The silicide need to be optimally annealed in order to obtain a good ratio of metal silicide to silicon in the gate structure Titanium silicide is formed by depositing PVD Ti on silicon substrates followed by annealing process. Anneals were carried out in an N2 ambient and resulted in a thin TiN layer on the silicide surface. For cobalt cilicide, a CVD cobalt layer was deposited on-top silicon at 450°C, and after annealing the structure, Co2Si phase was formed. And at 800°C the high resistivity CoSi phase formed. As we continued to increase the anneal temperature to 950°C, CoSi2 layer is formed. The high temperature required to form a silicide and the non existence of the Co2Si phase are attributed to the oxide at the interface. It is found that cobalt silicide grew faster and deeper to the silicon, thus saving a lot of time and cost. The succeding experiments also show that cobalt silicide has better electrical properties such as sheet resistance, capacitance and electron mobility. The transistor fabrication process was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module

Effect of process parameter variations on threshold voltage in 45nm NMOS device

Taguchi method was used to optimize of the effect process parameter variations on threshold voltage in 45nm NMOS device. In this paper, there are four process parameters (factors) were used, which are Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. The virtual fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were combined with Taguchi method to aid in design and optimizer the process parameters. Threshold voltage (VTH) results were used as the evaluation variables. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were then successfully verified with ATHENA and ATLASs simulator. In this research, oxide growth temperature was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.15V.

Characterization and optimizations of silicide thickness in 45nm pMOS device

The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLASs simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is −0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

Effect of moisture on underfill interfacial adhesion and packages flexural strength in flip chip packaging

In this study, effect of various moisture condition on underfill interfacial adhesion loss were examined using C-SAM, 4-point flexural bend test, and cross sectional analysis. In addition, weight gain analysis was used to determine packages moisture absorption at preconditioning level. In order to understand mechanical properties degradation of underfill material, 4-point flexural bending test was used. Maximum flexure load to bend the FC packages was recorded. Failure mode then was categorized to 3 mode; mode 1 for die cracking, mode 2 for underfill cracking and mode 3 for the combination of mode 1 and mode 2. Selected units for every condition were cross sectioned and analyzed with their bend test graph to further understand FC packages breaking mechanisms. It was interesting to found that maximum flexure load was degraded after every moisture condition .The failure mode has changed from die cracking to underfill cracking. Furthermore, cross sectional analysis shows that underfill cracking failure mode has propagated from cohesive failure at fillet area to adhesive failure at underfill to substrate/die interfaces. As a conclusion, packages flexural strength degraded after moisture stressing with failure mode shows the underfill mechanical properties degradation is the one of the factor that degrades the flexure strength and decreases underfill interfacial adhesion

Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET

In this paper, Taguchi method was used to analyze of input process parameters variations on threshold voltage (VTH) in 45nm n-channel Metal Oxide Semiconductor device. The orthogonal array, the signal-to-noise ratio, and analysis of variance are employed to study the performance characteristics of a device. In this paper, there are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, S/D implant energy was identified as one of the process parameter that has the strongest effect on the response characteristics. While the halo implant dose was identified as an adjustment factor to get the nominal values of VTH for NMOS device equal to 0.289V at tox= 1.06nm.

Lesson study: Assessing pre-service teacher's performance of teaching chemistry

This paper will report on an effort to integrate the simulated-teaching Lesson Study approach in the chemistry teaching method course offered to the third year students in a science teacher education program. The integrated Lesson Study has promised to be an effective teacher development strategy focusing on developing the appropriate skills of teaching and continuous improvement of student performance in the classroom. A total of 44 pre-service teachers enrolled in the course were involved in the project. They were divided into eight groups based on their major and minorscience subjects. Each group of pre-service teachers conducted three cycles of Lesson Study for one topic of form four orform five chemistry syllabus. The improvement of simulated-teaching Lesson Study performance was measured at each cycle by using the instrument “Lesson Study Teacher Performance Assessment Form” (LSTPAF) that consisted of two parts: the performance of teacher candidate and participating students; gives the to talled measurement three times (three cycle) by the teacher educator and peer group member. In this study, Rasch Model is used to analyse data on teaching performance of teaching chemistry for each of Lesson Study cycle of each group of teachers selected. The assessment conducted during the teaching observation is perceived as a valuable experience thus enable them to evaluate and revise the lesson in detail especially the teaching of teacher candidate and participating students throughout the Lesson Study process in chemistry subject for secondary syllabus.