Ibrahim Ahmad

HF Etching of Sacrificial Spin-on Glass in Straight and Junctioned Microchannels for MEMS Microstructure Release

Sacrificial spin-on glass (SOG) etching in straight and junctioned microchannels using hydrofluoric acid (HF) was investigated. SOG etch rates in both reaction-dominant and diffusion-dominant regimes for various HF concentrations were studied. An etching model based on a non-first-order chemical reaction/steady-state diffusion etching mechanism is presented to compensate for the etching effect at the channel junction. Straight microchannels 1500 μm in length and various widths were fabricated on silicon substrate by coating a hardened photoresist layer over rectangular-shaped SOG layers. Junctioned microchannels were fabricated on silicon by filling SOG into deep reactive ion etching (DRIE)-etched microchannels. The samples were time-etched in HF solution and etch-front propagation was observed under an optical microscope. It is observed that the SOG etch rate is linear in the reaction-limited region and drops approximately 70% in the diffusion-limited region. The SOG etch rate in microchannels is independent of channel width and depth. The SOG etch rate at the T-junction is 0.67 times lower than its etch rate in straight channels due to the instantaneous drop in HF concentration. This behavior is well embodied by the presented numerical model. Finally, 5% HF is suitable for release etch due to its acceptable etch rate while being less damaging to microelectromechanical system (MEMS) microstructures.

An efficient first order sigma delta modulator design

An efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65 nm CMOS technology. This study at first determines the non-idealities of sigma delta modulator. The non-idealities investigated here are clock jitter noise that effects the input signal and increases total error power; then the thermal noise of switches caused by the random fluctuation of carrier that increases the total noise power. Thereafter, circuit leakage causes the limited DC gain and affects signal to noise ratio. Moreover, limited slew rate and gain bandwidth of op-amp, which are both regarded as non-linear gain, reduce signal to noise sum distortion ratio. Based on optimum circuit simulation, the non-idealities are reduced by using folded cascode op-amp at integrator stage with DC gain of 65 dB, slew rate of 3.76 V/mus, and gain bandwidth with 40 MHz. Finally, a first order sigma delta modulator with 8 bit resolution, 64 oversampling ratio as well as power supply of plusmn2.5 V is successfully designed using PSPICE simulation tool, which can be implemented for practical usage.

Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG) as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP) as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

Characterisation of polysilicon gate microstructures for 0.5 μm CMOS devices using transmission electron microscopy and atomic force microscopy images

Abstract This paper considers two different doping methods and compares their impact on the polysilicon’s microstructures when doped with phosphorous by using the transmission electron microscopy (TEM) and atomic force microscopy (AFM) images. The two doping methods considered are the in situ (or also known as thermal diffusion) and ion implantation. For the in situ method, phosphane (PH 3 ) with concentration of 1.8×10 20 xa0cm −3 was used while for the ion implantation, two different doses were used: 2.0×10 16 and 3×10 16 xa0cm −2 at 40xa0keV. The surface roughness of the polysilicon microstructure obtained via the in situ method measures between 12 and 26xa0nm with a peak roughness of 14xa0nm and grain size of 4xa0μm. As for the ion implantation method, at lower dose the microstructure surface roughness varies from 12 to 46xa0nm with a peak roughness of 34xa0nm while the grain size measures between 100 and 200xa0nm. At higher dose, the surface roughness varies from 12 to 48xa0nm and the peak roughness measuring at 36xa0nm. The grain size was between 500 and 800xa0nm. Comparing the TEM and AFM images of the in situ method to ion implantation method reveals that the polysilicon doped by the in situ method has larger grains, smoother and thinner microstructure properties resulting in better gate morphology control.

Study of Lifetime Prediction of N-MOS Transistor Due to Hot Carrier Effect

This study discusses a technique to define the reliability and predict the lifetime of NMOS transistor through stressing and analyzing process by using Agilent 4070 Series equipment and xHCI software at wafer level. The stressing process uses direct current stressing method while Takeda and Hu models are used in analysis process. The result of the experiment is in the graph form and it depends on the analysis method which is can be referred to both Takeda and Hu models. The minimum lifetime prediction was 860 hours by using Takeda model as compared to 790 hours using Hu model. The different result between Takeda and Hu model was about 8% only and this allowed both Takeda and Hu models to be used in lifetime prediction of NMOS transistor. For the conclusion, by referring to this lifetime prediction graph, any operating voltage of transistor can predict the lifetime.

MATLAB based image analysis software for characterization of microstructure materials

This paper presents MATLAB based image analysis software specially developed to perform characteristic analysis of microstructures images such as the Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Scanning Electron Microscopy (SEM) etc. The developed software is user-friendly with graphical user interface (GUI), allows dynamic 2D and 3D visualization and performs standard statistical analysis to analyze the microstructure morphology automatically. Two examples are given to show the effectiveness of the software.

TCAD Simulation of STI Stress Effect on Active Length for 130nm Technology

In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterras 130 nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5 um to 0.34 um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data.

Effect of moisture on underfill interfacial adhesion and packages flexural strength in flip chip packaging

In this study, effect of various moisture condition on underfill interfacial adhesion loss were examined using C-SAM, 4-point flexural bend test, and cross sectional analysis. In addition, weight gain analysis was used to determine packages moisture absorption at preconditioning level. In order to understand mechanical properties degradation of underfill material, 4-point flexural bending test was used. Maximum flexure load to bend the FC packages was recorded. Failure mode then was categorized to 3 mode; mode 1 for die cracking, mode 2 for underfill cracking and mode 3 for the combination of mode 1 and mode 2. Selected units for every condition were cross sectioned and analyzed with their bend test graph to further understand FC packages breaking mechanisms. It was interesting to found that maximum flexure load was degraded after every moisture condition .The failure mode has changed from die cracking to underfill cracking. Furthermore, cross sectional analysis shows that underfill cracking failure mode has propagated from cohesive failure at fillet area to adhesive failure at underfill to substrate/die interfaces. As a conclusion, packages flexural strength degraded after moisture stressing with failure mode shows the underfill mechanical properties degradation is the one of the factor that degrades the flexure strength and decreases underfill interfacial adhesion

Pb-free BGA Solder Joint Reliability Improvement with Sn3.5Ag Solder Alloy on Ni/Au Finish

In this work, Sn3.5Ag solder alloy was being studied for the purpose of Pb-free solder joint reliability improvement over conventional Sn3.8AgO.7Cu solder balls on Ball Grid Array (BGA) packages with Ni/Au pad finishing. The study was carried out in different levels. At individual solder joint level, Sn3.5Ag showed no intermetallic brittle failure in cold ball pull test even up to 6times multiple reflow and 168 hrs high temperature storage for TBGA & TePBGA, and 504 hrs high temperature storage for PBGA Spanish Oak. In contrast, 70-100% of the failure mode of SAC387 was brittle failure. At package level, Sn3.5Ag survived 8~10x more drop cycles than SAC387 in tray drop and packing drop tests. These results indicate that the mechanical strength of Sn3.5Ag on Ni/Au pad is considerably stronger than that of SAC387. The difference in mechanical strength between the two alloys was correlated to their microstructures. At the same time, board level solder joint reliability tests such as thermal cycling and mechanical bend test were carried out. Sn3.5Ag showed better or similar performance as SAC387.

The influence of junction formation process variables on diffusion sheet resistance using statistical design of experiment methodology

The statistical design of experiments technique was used to study the influence of junction formation process variables on the diffusion sheet resistance. A two-level screening experiment with 2/sup 3/ factorial design was used to evaluate three process variables in eight combination runs. The factors were BF/sub 2/ and Ar implantation dose, drive-in temperature and drive-in time. Variance analysis was used to analyze the data and we found that all of the main variables were important for arsenic implanted wafers but only the drive-in temperature factor was important for boron implanted wafers. We also discovered that there was no significant interaction between the factors. For arsenic implanted wafers, which were driven-in at 950/spl deg/C, the measured sheet resistances were at between 110 and 130 /spl Omega///spl square/ while for wafers which were driven-in at 850/spl deg/C, the sheet resistances were measured at between 60 and 90 /spl Omega///spl square/. For boron implanted wafers, the measured sheet resistance values were found to be constant at about 30 /spl Omega///spl square/, regardless of drive-in temperature. The experimental data were used in regression equations to model the sheet resistance. By this, we have illustrated how the statistical design of experiments methodology can be used effectively in order to control the process performance.