Azzedin D. Es-Sakhi

Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design

This paper presents the concept of a new field effect transistor (FET) based on ferroelectric insulator. The proposed design is named Silicon-on-Ferroelectric Insulator (SOF) FET. The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The design proposes that by burying a layer ferroelectric insulator inside bulk silicon substrate an effective negative capacitance (NC) can be achieved. The NC effect can provide internal signal boosting. It is demonstrated that by carefully selecting thickness of the ferroelectric film inside the device the subthreshold swing and the threshold voltage can be lowered. Lower subthreshold swing is a prime requirement for ultra-low-power design.

Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)

This paper presents the current-voltage (I-V) characteristic of our proposed Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOF-FET). The proposed SOF-FET is based on the concept of silicon-on-insulator (SOI) device technology and it utilizes a negative capacitance that can be achieved by inserting a layer of ferroelectric insulator inside the bulk silicon substrate of the device. The negative capacitance (NC) effect can provide an internal signal boosting that leads to steeper subthreshold slope, which is the prime requirement for ultra-low-power circuit operation. Here we have analyzed the impacts of channel doping profile on the behavior of the proposed SOF-FET. The major focus of this paper is the investigation of the current-voltage (I-V) characteristics of the proposed SOF-FET. Here the (I-V) characteristics of both the subthreshold and the saturation regions of the proposed device have been derived.

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO2 with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device. The concept of a new field effect transistor based on ferroelectric insulator.The SOF-FET structure offers better switching performance due to inherent low short channel effect and low subthreshold swing.The design combines the concept of the inherent negative capacitance in ferroelectric material with the partially depleted silicon-on-insulator structure.A model is derived to show that the subthreshold swing and the threshold voltage of the proposed structure are dependent on the oxide materials, ferroelectric thicknesses and doping profiles.

Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET)

Tunnel Field Effect Transistor (TFET) based on Band-to-Band tunneling mechanism is a revolutionary device technology that has a very strong potential to break the thermodynamic barrier of conventional FETs and provide a very steep subthreshold slope. TFETs would also allow further reduction of channel length to extend the Moores law. TFETs in general suffer from low ON-state current (ION). In this paper, we propose a new TFET structure to increase the drain to source current of the tunneling devices. The design is based on single-walled carbon nanotubes (SWCNTs). The idea is to provide multiple SWCNTs as tunneling path. We demonstrated the concept with three SWCNTs. By having three tunneling paths in a single device higher ON-current can be achieved. In this study, the diameter of the tubes and the gate oxide thickness are adjusted to obtain a high ION.

Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET

This paper presents a study of the structure and the characteristics of the emerging device - SOI-FinFET. Close form models are developed to estimate the values of the device capacitances. Using these capacitance models, an expression for subthreshold swing of the SOI-FinFET is derived. These models have been used to investigate the behavior of SOI-FinFET in the subthreshold region, the I-V characteristics, and the drain induced barrier lowering (DIBL). These approximations are based on the structure and the internal capacitive coupling of SOI-FinFET. The effects of doping attenuation in the channel, charge trapping in the insulator, and some other factors are not taken into consideration, because the focus of this paper is to investigate the impact of the geometric dimensions and related factors on the behavior and the operation of SOI-FinFET. The channel of SOI-FinFET is either undoped or lightly doped. In addition to analyzing the impact of various geometric parameters on the behavior of the device, the developed models and the presented analysis would be of great importance for future CAD tool development and design automation. It is observed that by optimizing these dimensional factors, a subthreshold swing (S) value very close to 60mV/decade can be achieved for SOI-FinFET. Display Omitted Modeling and evaluation of the intrinsic capacitance components of SOI-FinFET.Analytical approach to model and estimate the subthreshold swing of SOI-FinFET.The aspect ratio Fin-height/Fin-width (AR) can be improved for ULP applications.High AR the transistor effective area increases, which enhance driving capability.A high aspect ratio will give a lower DIBL and lower subthreshold swing.

Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET)

This paper presents the concept of a new field effect transistor (FET) based on ferroelectric insulator. The proposed design is a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material with the design of a partially depleted silicon-on-insulator (PDSOI) device. In this structure we propose to develop a negative capacitance (NC) in the body of the device by utilizing the inherent hysteresis behavior of ferroelectric material, which would be inserted as a buried insulator layer in between silicon substrate and a thin buffer layer in a PDSOI device structure. In addition to introduce the concept of a new ferroelectric insulator based SOI device structure, this paper presents closed form models to calculate the subthreshold swing of the proposed device. It is demonstrated that by carefully optimizing the thickness of the ferroelectric film, dielectric property of the insulator, and the channel thickness, the device can be operated at a subthreshold swing below 60mV/decade that represent the theoretical thermodynamic limit of conventional MOSFET performance.

Analytical model to estimate the subthreshold swing of SOI FinFET

This paper presents an analytical model to approximate the subthreshold swing of a SOI-FinFET device. The model considers only the capacitive coupling inside the structure of the device and does not take the doping attenuation of the channel into consideration because the channel of SOI-FinFET is either undoped or lightly doped. The devolved model can be used to analyze the impacts of various device parameters on the subthreshold behavior of SOI-FinFET. It is deducted that by optimizing the internal geometric parameters it is possible to achieve a subthreshold swing (S) or inverse subthreshold slope value close to 60mv/decade for SOI-FinFET. For the existing and emerging MOS devices the value of S is much higher than 60mv/decade (the theoretical minimum for silicon devices).

Analysis of optical and electronic properties of MoS2 for optoelectronics and FET applications

Molybdenum disulfide (MoS2) is considered as a promising alternative to conventional semiconductor materials that used in the IC industry because of its novel properties. In this paper, we explore the optical and electronic properties of MoS2 for photodetector and transistors applications. This simulation is done using ‘DFT materials properties simulator’. Our findings show that mono- and multi-layer MoS2 is suitable for conventional and tunnel FET applications due to direct and indirect band-gap respectively. The bulk MoS2 crystal, which are composed of stacked layers have indirect bandgap and mono-layer MoS2 crystal form direct bandgap at the K-point of Brillouin zone. Indirect bandgap of bulk MoS2 crystal implies that phonons need to be involved in band-to-band tunneling (BTBT) process. Degenerately doped semiconductor, which is basically spinning the Fermi level, changing the DOS profile, and thinning the indirect bandgap that allow tunneling from valence band to conduction band. The optical properties of MoS2 is explored in terms of Absorption coefficient, extinction coefficient and refractive index. Our results shows that a MoS2 based photodetector can be fabricate to detect light in the visible range (below 500nm). It is also observed that the MoS2 is most sensitive for the light of wavelength 450nm.Molybdenum disulfide (MoS2) is considered as a promising alternative to conventional semiconductor materials that used in the IC industry because of its novel properties. In this paper, we explore the optical and electronic properties of MoS2 for photodetector and transistors applications. This simulation is done using ‘DFT materials properties simulator’. Our findings show that mono- and multi-layer MoS2 is suitable for conventional and tunnel FET applications due to direct and indirect band-gap respectively. The bulk MoS2 crystal, which are composed of stacked layers have indirect bandgap and mono-layer MoS2 crystal form direct bandgap at the K-point of Brillouin zone. Indirect bandgap of bulk MoS2 crystal implies that phonons need to be involved in band-to-band tunneling (BTBT) process. Degenerately doped semiconductor, which is basically spinning the Fermi level, changing the DOS profile, and thinning the indirect bandgap that allow tunneling from valence band to conduction band. The optical propertie...

Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits

Local heating happens faster than chip-wide thermal spikes. This can cause performance and reliability issues in high density ICs. This type of thermal effect is critical in subthreshold circuit designs. To mitigate the thermal effect, we are employing a new nodal thermal management scheme by utilizing a new multi-Vt transistor. Many circuits are implemented using multi-Vt transistors to minimize leakage power and thermal effect while optimizing delay. In this paper, we present multi-Vt circuit design using our recently proposed Silicon on ferroelectric insulator FET (SOFFET) based circuits. SOFFET has shown tremendous potential for various ultra-low-power (ULP) applications. In addition, it provides high-performance multi-Vt design, strong threshold voltage control, lower supply voltage, sub-60mV/decade operation, higher current drive, and better short-channel characteristics. The flexibility to control the threshold voltage via back gate has created tremendous interest in double-gated SOFFETs for nodal thermal control and next generation high speed and low power IC designs.

Multilayer graphene nanoribbon based BioFET sensor design

High performance biofunctionalized field effect transistors (BioFETs) use nanoscale electronic materials such as silicon nanowires (SiNWs), carbon nanotubes (CNT) and graphene for the sensing application. Specific focus will be on high-performance, low-cost, scalable, and reliable biofunctionalized field effect transistor (BioFET) based on graphene. We attempted to build the graphene based sensing device on silicon substrate. We are proposing a biosensor where graphene could be used as a channel material and extended gate for ion detection. The idea is to combine existing concepts of biosensors based on ion-sensitive field-effect transistor (ISFET) and chemically modified field-effect transistors (CHEMFET), and implement it on a new Graphene nanoribbons (GNR) based BioFET. Both ISFET and CHEMFET concepts are based on floating-gate transistor operation similar to that of Flash memory design. In this paper, we will explore regular transistor based graphene FET (GFET) intended for biosensing application.