Nahid M. Hossain

Multilayer graphene nanoribbon floating gate transistor for flash memory

Floating gate transistor is the basic building block of nonvolatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. As silicon based integrated circuit technologies are approaching the limits of scaling, carbon based nanoelectronic devices are emerging as the future platform for low power, low cost, high performance and environment friendly circuits and systems. In this paper, a new concept of carbon nanostructure based floating gate transistor is presented. We have demonstrated a design using multilayer graphene nanoribbon (MLGNR) as the channel material and carbon nanotube (CNT) as the floating gate in the floating gate transistor. We have performed analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. We have observed that the proposed floating gate transistor can be operated at a much lower voltage compared to the conventional silicon based floating gate devices.

Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials

Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias.

Analysis of radiation effect on the threshold voltage of flash memory device

Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The the operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this letter, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model.

Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation

Flash memory based on floating gate transistor is the most widely used memory technology in modern microelectronic applications. We recently proposed a new concept of multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT) based floating gate transistor design for future nanoscale flash memory technology. In this paper, we analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide.

Analysis of the properties of ZnO nanoparticle for emerging applications in nanoscale domains

Semiconductor nanoparticles are getting significant attention due to their diverse applications in optoelectronics, photovoltaics, photonics, transparent electronics and other nanoelectronic devices. Zinc Oxide (ZnO) is one of the promising nanoparticles with a unique set of material, physical, optical, electrical and thermal properties. This paper investigates diverse potential applications and unique properties of ZnO nanoparticles. The analysis reveals that ZnO can be easily used as an n-type heavily doped oxide semiconductor and its bandgap is wide enough for various applications. We have performed a set of analysis to study the electronic, optical, thermal and material properties of ZnO to understand its behavior at nanoscale dimension and its potential roles in different devices.

Graphene and CNT based flash memory: Impacts of scaling control and tunnel oxide thickness

For flash memory devices the thicknesses of the control and tunneling oxides in the floating gate transistor (FGT) are crtical parameters. We recently proposed a floating gate transstor using multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In this paper, we have analyzed the impacts of scaling the thickness of the control and tunneling oxides in the proposed MLGNR/CNT based FGT. According to ITRS, semiconductor industry has already adopted 6nm thick tunneling oxide for 18-nm and 22-nm technology nodes. By 2020, technology is expected to move to 10nm node, and 5nm tunnel oxide is predicted for 8nm-14nm nodes. For less than 20nm technology nodes, ultra-thin tunnel oxide would lead to higher tunneling current density that will affect the reliability of the flash memory cell. Based on our analysis we have provided some recommendations about the scaling of oxide thickness in the proposed MLGNR/CNT floating gate transistor.

Thermal aware Graphene based Through Silicon Via design for 3D IC

Heat transfer and consistent power delivery are the two most critical issues in 3D stacked IC technology. In order to ensure consistent and reliable power delivery to all the components of the 3D stacked IC while suppressing the power supply noise to a minimum level, a highly efficient power distribution network is essential. But complex thermal and power networks weaken signal integrity in 3D IC. Through Silicon Via (TSV) is an important limiting factor for 3D integrated circuit (IC) performance. TSVs are used mainly for power distribution, signal delivery, clock distribution and heat conduction. In this paper, a new design of multi-layer Graphene nanoribbon (MLGNR) based TSV for 3D IC has been proposed. Power distribution and thermal management of the TSV has been investigated. Graphene has unique electrical properties and superior heat conduction capability. These exceptional characteristics make the MLGNR bundle a perfect candidate for TSV design in 3D IC. The results and analysis indicate that MLGNR would perform better than copper (Cu) and carbon naotube (CNT) based TSVs.

Impacts of different shapes of through-silicon-via core on 3D IC performance

In 3D IC technology, Through Silicon Via (TSV) is the primary medium used to distribute power and signal between layers of chips. Placement of a large number of TSVs in close vicinity leads to performance degradation due to interferences and crosstalk. The core of a TSV is usually circular column shape. In this paper, different shape for the core of the TSV is investigated to find the best possible shape and structure that can reduce different losses like return loss and insertion loss in the TSV design. We have explored circular, rectangular, octagonal and hexadecagonal shapes for the core. Simulation results indicate that rectangular TSVs performance is better than other polygonal TSVs and conventional circular TSV. We have also performed simulation to estimate the E-field and H-field coupling between two TSVs. These two are important performance parameters for TSV. The performance of the TSVs seems to degrade with the increasing number of segments in the polygon representing its shape.

Emerging STT-MRAM circuit and architecture co-design in 45nm technology

The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPUs. The most capable Nonvolatile memory (NVM) component is STT-MRAM. There is a demand to improve efficient circuit and architecture to compete with the existing NVM technologies. Low energy consumption is achieved to write and read into MTJ. This provides the Circuit and Architecture Co-design of STT-MRAM. Our contributions are: One bit STT-MRAM circuit design and SPICE simulation, Monte Carlo simulation of access transistor, 8×8 array/architecture of STT-MRAM is implemented by the single cell.

Error free sense amplifier circuit design for STT-MRAM nonvolatile memory

The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPUs. The most capable NVM component is STT-MRAM, which enhances the performance by 3.3 nS access time. It has strong radiation hardness, higher integrity and maximum endurance compared to SRAM. The power consumption of STT-MRAM is decreased by an order of magnitude by reducing the writing current. In this article, a new error free sense amplifier circuit is proposed. The detail analysis of the sense amplifier circuit is provided here. Finally, the performance of the proposed the sense amplifier is compared with existing sense amplifiers.