B. Blampey

Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters

The speed of integrated circuits is increasingly fixed by interconnect performances. To address this issue, the development of new back-end of line technology schemes and materials should be driven by predictions of associated benefits. A new tool was developed and coupled to electromagnetic software to carry out time domain simulations. As a result, the dependences of interconnect performances on process parameters and design rules were extracted for the 65 nm and 45 nm technology nodes.

Dielectric Loss Effects on the Modeling of Interconnect Responses for the 45 nm Node

Recent complex permittivity measurements of low-k porous SiOCH have outlined that dielectric losses cannot be considered negligible. Furthermore those results show apparently non causal dependence of real and imaginary parts of the permittivity with frequency. This behaviour leads to inconsistent models of interconnects, as illustrated in this paper regarding the 45 nm technology node. Time domain simulations using such models induce errors, especially on the propagation delay. To give a factual vision of this purpose, two different dielectric loss models have been studied to prove the requirement of the greatest care to evaluate interconnect responses.

Delay and Crosstalk on Future 32 nm Node Interconnects: Impact of ULK-Air-Gap Architecture

With technological developments towards 32 nm node ICs, interconnects effects have become fundamental on integrated circuits performances. Signal propagation will in particular be affected by complexity of technological stacks. In order to face integration and performance issues, air gap architecture constitutes a potential alternative to porous dielectric materials. After showing that air gap addresses the challenges on delay time for considered node, dimension effects corresponding to several kinds of applications will be analyzed in order to extract limits of integration regarding time-domain performances in terms of delay and crosstalk

Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact

Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL performances. A rigorous high-frequency electromagnetic approach including the scattering effects on Cu line resistance was developed for coupled narrow interconnects to analyze the actual benefits of these innovations for different signal types covering application range from logic to I/O. Effects of advanced metallization (ALD thin barriers), low-k insulators (porous ULKs, low-k barriers), and innovative architectures (hybrid stacks, air gaps, self-aligned barriers) on signal propagation performance were quantified, resulting in an effective process selection for the 45 nm technological node and below.

Performance predictions of prospective air gap architectures for the 22 nm node

With technological developments towards 22 nm node ICs, integration and process issues will be critical for signal propagation on interconnects. Air gap architecture, as a potential alternative to porous dielectrics, is thus analyzed for two SiO2 sacrificial approaches. Thanks to electromagnetic and time-domain simulations, extraction of barrier properties and dimensions limits regarding capacitance, delay and crosstalk parameters is realized, leading to the proposal of a specific stack as a global solution to this problematic.

Impact of ULK Dielectric Loss on Interconnect Response for 45 nm Node Integrated Circuits

New materials such as dielectrics with ultra low permittivity are required to improve interconnect performance for future ICs technology nodes. Porous dielectric materials, as SiOCH, used for the 45 nm technology are very prone to damage during integration process, degrading their permittivity and severely increasing their loss tangent. Theses dielectric losses have to be precisely taken into account in order to accurately simulate the propagation effects along interconnects and to predict delay and crosstalk. Thus fine large-band extraction of complex permittivity must be achieved in respect to physical consistence of signals. This study aims at accurately evaluate the impact of dielectric degradation on interconnects electrical performance. Moreover it will be outlined, using two different ICs configurations, that the accurately on the prediction of interconnect performance needs adequate dielectric models.