B. Cheng

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.

Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V/sub T/ adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes.

Analog device design for low power mixed mode applications in deep submicron CMOS technology

Analog device design in the deep sub-micron regime is particularly challenging due to conflicting device performance requirements and the circuit requirements in analog applications. It is shown that novel single pocket devices improve the intrinsic analog performance compared to the conventional super steep retrograde devices, within the constraints imposed by circuit requirements. The effect of gate oxide thickness variation on the analog performance of the novel single pocket and conventional super steep retrograde n-channel MOSFETs is also evaluated. It is shown that for constraints on power supply scaling, single pocket structures offer a better option for low-power analog applications.

Design considerations of high-/spl kappa/ gate dielectrics for sub-0.1-/spl mu/m MOSFET's

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation.

A temperature-dependent MOSFET inversion layer carrier mobility model for device and circuit simulation

A new semi-empirical model for electron and hole mobilities in MOSFET inversion layers is proposed. For the first time, the magnitude of the key parameter /spl eta/, which defines the effective transverse field, is found to be a continuous function of temperature for both electrons and holes. The effective transverse field dependences of the universal mobility curves are observed to differ between the electrons and holes, particularly at low temperatures. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics over a temperature range from 77 K to 313 K.

100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si/sub 3/N/sub 4/ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO/sub 2/ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si/sub 3/N/sub 4/ barrier (2.1 eV) is lower than the Si-SiO/sub 2/ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO/sub 2/ MOSFETs.

Deep sub-micron CMOS device design for low power analog applications

Signal swing, power and device performance requirements for analog applications result in trade-offs for scaled MOSFET design. This paper presents a comprehensive study on optimization of deep sub-micron NMOS device for low power analog applications. It is shown that novel channel engineering is essential along with thin gate oxides and shallow junctions for improving the device analog performance.

Improvement of Flicker Noise in Lateral Asymmetric Channel N-MOSFETs for Sub-micron Analog Applications

Flicker noise in Lateral Asymmetric Channel (LAC) N-MOSFETs is investigated in details. It is found that in comparison to conventional devices, LAC devices have significantly lower 1/f noise even in deep submicron channel lengths. While the higher transconductance and the current drive can be attributed to the higher average electron velocity in the LAC devices, the lower noise is due to the smaller integrated inversion charges in the channel in the LAC devices.