P. Vande Voorde

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

Boron diffusion and penetration in ultrathin oxide with poly-Si gate

Boron penetration through thin gate oxide down to 17 /spl Aring/ is investigated in this work. Boron penetration is characterized by the amount of flat band shift in a MOS capacitor. The effective diffusion coefficient of boron in these thin oxides is found to be higher than in thicker oxides. The introduction of a moderate dose of fluorine (1/spl times/10/sup 15/ cm/sup -2/) during gate doping enhances boron penetration in these thin oxides. Compared to as-deposited polycrystalline silicon (poly-Si), crystallized amorphous silicon (/spl alpha/-Si) films display slower boron diffusion in the gate and reduce enhancement of boron penetration due to fluorine. However, crystallized /spl alpha/-Si gate also reduces the amount of dopant activation and leads to extra gate depletion. The tradeoff between dopant activation and boron penetration is discussed.

Density-gradient analysis of MOS tunneling

The density-gradient description of quantum transport is applied to the analysis of tunneling phenomena in ultrathin (<25 /spl Aring/) oxide MOS capacitors. Both electron and hole tunneling are included in the one-dimensional (1-D) analysis and two new refinements to density-gradient theory are introduced, one relating to the treatment of Shockley-Read-Hall recombination and the other a modification of the tunneling boundary conditions to account for the semiconductor bandgap. Detailed comparisons are made with experimental current-voltage (I-V) data for samples with both n/sup +/ and p/sup +/ polysilicon gates and all of the features of the data are found to be understandable within the density-gradient framework. Besides providing new understanding of these experiments, these results show that the density-gradient approach can be of great value for engineering-oriented device analysis in quantum regimes.

A high-speed bipolar technology featuring self-aligned single-poly base and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2- mu m emitter-base polysilicon contact separation. A 0.4- mu m emitter width is achieved with conventional 0.8- mu m optical lithography. Scaling of the emitter width of 0.3 mu m has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 mu m has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f/sub t/ as high as 33.8 GHz.<<ETX>>

Indium transient enhanced diffusion

Indium, an acceptor dopant in silicon, is a large atom with a low diffusion coefficient potentially suitable for doping the channel of transistors. Systematic experiments are described which measure the susceptibility of indium to transient enhanced diffusion caused by ion implant damage introduced during the transistor fabrication process. We find that indium diffusion is dramatically enhanced by a source of interstitials and that the amount of enhancement is comparable to that seen for boron. Indium is preferable as a channel dopant not because of its diffusion behavior, but rather because a narrow ion implanted distribution can be obtained using the heavy indium ion, giving a more steeply retrograde profile than can be achieved by boron doping. These results help clarify the physics of indium and boron doping in small devices.

Design considerations of high-/spl kappa/ gate dielectrics for sub-0.1-/spl mu/m MOSFET's

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation.

A new device interconnect scheme for sub-micron VLSI

A new device interconnect scheme for sub-micron VLSI has been developed. In this technology N+ and P+ diffusions and N+ and P+ gates of a CMOS process can be directly connected in any combination desired without the use of contacts or aluminum. This provides much improved packing density over conventional processes. Since the source/drain (S/D) contacts can extend over the field oxide regions, minimum sized S/D diffusion areas can be used. This leads to a significant decrease in parasitic diffusion capacitances relative to other processes. Several devices can share one contact when they need to communicate, and so the total number of contacts can be greatly reduced. Since the contacts do not have to be limited to minimum dimensions a relaxation of sub-micron contact processing is achieved. In addition the use of a self-aligned silicide reduces interconnect and other device parasitic resistances. NMOS and PMOS devices have been successfully fabricated using this process.

Double-diffused graded SiGe-base bipolar transistors

Self-aligned SiGe/Si bipolar transistors have been fabricated using a single-polysilicon, double-diffused process with the base in a graded SiGe layer to improve base transit time. To remain compatible with homojunction bipolar technology, undoped SiGe base and Si emitter layers were deposited by selective epitaxy at temperatures of 700-750/spl deg/C in a commercial epitaxial reactor. Maximum cutoff frequencies of 40 and 50 GHz were observed for devices with collector-emitter breakdown voltages (BV/sub CEO/) of 4.2 and 3.0 V, respectively. Preliminary results indicate that the addition of Ge to the base of these transistors did not degrade the long-term device reliability. >

Hybrid simulation and sensitivity analysis for advanced bipolar device design and process development

A methodology for using SUPREM, PISCES, and SPICE to simulate the AC characteristics of advanced bipolar devices is described. Accurate predictions for f/sub T/ and f/sub MAX/ to process variations are calculated. These techniques can be used to study the sensitivity of device performance to variations in the device structure or doping profiles. Analysis of charge storage in the device structure using PISCES yields estimates for the various delay components. The impact ionization models in PISCES can be used to estimate the breakdown properties of a given device structure or doping profile.<<ETX>>

Density-gradient analysis of tunneling in MOS structures with ultra-thin oxides

Quantum transport theory in the density-gradient approximation is applied to the analysis of tunneling phenomena in ultra-thin oxide (<25 A) MOS structures. Detailed comparisons are made with experimental I-V data for samples with both n/sup +/ and p/sup +/ polysilicon gates and all of the features of this data are found to be understandable within the density-gradient framework. Besides providing new understanding of the experiments, these results show the density-gradient approach to be useful for engineering-oriented device analysis in quantum regimes with current flow.