B. Hoefflinger

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

Complex 3D CMOS circuits based on a triple-decker cell

We present circuit design concepts for a vertically integrated process. This process with its three stacked transistor channels leads to the very efficient basic circuits: Inverter, Selector and NAND2. These elements are used to build a cell library with standard elements like NOR, Latches, Flip-flops etc. Special macro-blocks as Multiplier, SRAM, CAM complete the circuit library. Area requirements for static CMOS logic ranges from 50% down to 25% compared to two-dimensional CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the three-dimensional CMOS process.

Model and performance of hot-electron MOS transistors for VLSI

VLSI reduces the dimensions of MOS transistors so far that the product of channel lengthLand hot-electron critical field ECbecomes comparable to or smaller than the transistor operating voltages. These transistors are classified as hot-electron MOS (HEMOS) transistors. On the basis of a hyperbolic velocity-field characteristic, a powerful nonlinear analytical model both for conductive and capacitive contributions is presented, which covers the triode and saturation regions continuously. The crucial parameter is the pinch-off field EG, for which a sensitive measurement technique is described. Static and dynamic simulations are in good agreement with 2-µm transistors and circuits, self-aligned by ion implantation. Expressions are developed for transistor transconductance, output resistance, available voltage gain, and effective input capacitance as well as inverter supply voltage, threshold voltages, ratio, noise margin, power dissipation, and delay time. These quantities are in terms of the characteristic product of channel lengthLand pinch-off field EGso that the effects of scaling into the submicron regime can be predicted as demonstrated by the design parameter set for a 5-fJ inverter with a 0.5-µm HEMOS driver transistor.

Model and performance of hot-electron MOS transistors for high-speed, low power LSI

An analytical model is presented for a MOS transistor, whose channel length L is so short that the product of L and the hot-electron critical field ECis smaller than the operating voltages. Static and dynamic charateristics are tested, in particular by using an SEM in the stroboscopic voltage contrast mode. Simple expressions for transconductance, output resistance, available voltage gain, input capacitance, supply and threshold voltage, noise margins, power and delay allow quantitative scaling into the submicron regime.

Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors

An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.

Sub-threshold and active-region characterization of ion-implanted buried-channel MOS transistors

The drain current versus gate voltage characteristics of ion-implanted buried-channel MOS transistors were measured and compared with a theory based on the in-depth impurity, mobile carrier, potential and mobility distribution. In more heavily implanted transistors, a characteristic sub-threshold current almost independent of gate voltage is obtained both experimentally and theoretically. For these cases, a new definition of threshold voltage is suggested. According to their potential distribution at threshold, implanted transistors are classified into three groups. The depths and widths of buried channels fall into the transition region from surface to bulk carrier mobility. Models for the mobility distribution including surface and impurity scattering as well as field dependence were used to calculate the active-region conductance.