G. Zimmer

Model and performance of hot-electron MOS transistors for VLSI

VLSI reduces the dimensions of MOS transistors so far that the product of channel length L and hot-electron critical field E C becomes comparable to or smaller than the transistor operating voltages. These transistors are classified as hot-electron MOS (HEMOS) transistors. On the basis of a hyperbolic velocity-field characteristic, a powerful nonlinear analytical model both for conductive and capacitive contributions is presented, which covers the triode and saturation regions continuously. The crucial parameter is the pinch-off field E G , for which a sensitive measurement technique is described. Static and dynamic simulations are in good agreement with 2-µm transistors and circuits, self-aligned by ion implantation. Expressions are developed for transistor transconductance, output resistance, available voltage gain, and effective input capacitance as well as inverter supply voltage, threshold voltages, ratio, noise margin, power dissipation, and delay time. These quantities are in terms of the characteristic product of channel length L and pinch-off field E G so that the effects of scaling into the submicron regime can be predicted as demonstrated by the design parameter set for a 5-fJ inverter with a 0.5-µm HEMOS driver transistor.

Dynamic SPICE-simulation of the electrothermal behavior of SOI MOSFET's

A nonlinear dynamic electrothermal model of the SOI MOSFET is implemented and used in SPICE3. This model is formulated as a set of algebraic and (partial) differential equations which is converted into a SPICE3 netlist automatically by a model translator. Neither is the simulator rewritten nor are SPICE device models implemented or changed. In this way, the presented approach supports effective model development. To show the electrothermal interaction, the SOI MOSFET model is applied to several static and dynamic simulations. The SPICE-simulation results of the thermal model are verified with the commercial finite-element simulator ANSYS. >

A novel tactile sensor system for heavy-load applications based on an integrated capacitive pressure sensor

We report on a tactile sensor system for heavy-load and heavy-duty applications. The sensor system is based on a surface-micromachined capacitive pressure sensor. A new packaging technique is presented that enables applications where large forces and rough operation environments prevail. Due to the CMOS compatibility, an efficient way to address and read out the sensor array can be realized. We present an application example that shows the enhanced versatility of heavy-load manipulators when using tactile sensors for manipulation tasks.

Integrated monolithic temperature sensors for acquisition and regulation

Abstract The monolithic integration of temperature sensors and sensor electronics considerably lowers system costs since the sensor signal can be processed and evaluated on the same chip. This paper describes the design of CMOS temperature sensors and associated acquisition circuitry. Problems connected with the high-temperature operation of analog MOS electronics are addressed and two temperature sensors based on two different principles are presented. Both sensors have been integrated with a switched-capacitor precision amplifier.

A compatible NMOS, CMOS metal gate process

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.

A novel readout technique for capacitive gas sensors

Abstract In this communication we propose a novel readout technique for capactive gas sensors. It uses periodically operated analog switches together with capacitors and operational amplifiers. These components are available in standard MOS and CMOS VLSI technologies and are, therefore, fully compatible with digital circuits. The technique provides not only sensor interfacing and signal amplification, but also offers the possibility of cancelling out offset and cross sensitivity. At the same time, the long-term d.c. drift has been eliminated.

BiCMOS: technology and circuit design

Abstract In this paper, the state-of-the-art of combined bipolar/CMOS (BiCMOS) technologies and circuit techniques is described. Examples of advanced BiCMOS technologies for various applications will be given, together with theoretical considerations which allow a comparison of the bipolar and MOS transistors. New BiCMOS circuit techniques are presented for analog and digital applications. It will be shown that the BiCMOS technology offers some significant advantages for analog circuits, such as operational amplifiers, low impedance output stages, and analog multipliers. Digital systems benefit from novel circuit techniques employed in buffers, interface circuits, logic gates, and large macrocells (e.g. multipliers, RAM, CAM). Several examples demonstrate the advantages of BiCMOS realizations over standard CMOS.

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV-2. The bipolar transistors have a low-resistance base contact. Current gain βFcan be set independently. For\beta_{F} = 90, the Early voltage isV_{A} = 110V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

Low power-low noise monolithic detector readout electronics

Design and performance of a CMOS charge sensitive amplifier-cable driver combination is being described. The single stage differential input amplifier has an open loop gain of 78 dB and a corner frequency of 7 kHz at 7.5 mW power dissipation. Power consumption of the amplifier can be steered by an external bias source. Using the bias input for fast turn on/off gives a settling time of 1 μs. The 1f noise charge contribution amounts to 400 + 11 Cpf electrons, independent of power consumption.

Integration of Detector Arrays and Readout Electronics on a Single Chip

This contribution addresses aspects of monolithic integration of detector arrays and readout electronics on a single silicon chip. It discusses the compatibility of silicon detectors with modern VLSI technologies which combined would yield high-performance low-power detection systems. Monolithic integration of detectors and detector arrays that would be compatible with todays integrated circuit (IC) technologies offers exciting prospects as it would combine detection and signal processing on a common substrate. This would result in vast savings of power, size, and wiring cost. Other benefits of such an approach include reduced interference and low cable loading of the detector. The block diagram of an envisioned integrated detector-signal processing system is shown.