B.M. Tenbroek

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-/spl mu/m SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage.

The effect of body contact series resistance on SOI CMOS amplifier stages

This paper examines some implications for analogue design of using body ties as a solution to the problem of floating body effects in partially-depleted (PD) SOI technologies. Measurements on H-gate body-tied structures in a 0.7-/spl mu/m SOI process indicate body-tie series resistances increasing into the M/spl Omega/ region. Both circuit simulation and measurement results reveal a delayed but sharper kink effect as this resistance increases. The consequences of this effect are shown in the context of a simple amplifier configuration, resulting in severe bias-dependent degradation in the small signal gain characteristics as the body-tie resistance enters the M/spl Omega/ region. It is deduced that imperfectly body tied devices may be worse for analogue design than using no body-tie at all.

Analogue design issues for SOI CMOS

There are many issues facing the analogue designer for mainstream VLSI SOI CMOS. Some are improvements (more useable bandwidth, less crosstalk), but many are difficulties. Thermal behaviour does not depend very strongly on the technology roadmap but possible matching problems do. The presence and degree of floating body behaviour hinges on specific process architecture as well as device layout. Except for kink effect coincident with saturation, most of these factors can be largely accommodated in design provided that the circuit level models and their extracted parameters are adequate. Without these, design becomes uncertain and requires time-consuming iterations incompatible with modern practices.

Measurement of buried oxide thermal conductivity for accurate electrothermal simulation of SOI device

Finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on insulator (SOI) devices. There is uncertainty about the conductivity of different forms of SiO/sub 2/, particularly that of buried oxides. This paper presents a novel approach to measure this conductivity, using structures that are compatible with standard bipolar or CMOS processes. Thermal conductivity values of 0.66 and 0.82 W/mK, respectively, were found for 300-nm BESOI and 420-nm SIMOX oxides at room temperature. The measured variations of thermal conducitivity with temperature agree well with bulk SiO/sub 2/ behavior. Better agreement between measurement and finite element simulation of MOSFET thermal resistance is obtained by using these extracted thermal conductivity values. It is also shown that the role of the silicon substrate in determining the thermal resistance of the device can be calculated using a simple analytical model. This is important when one wishes to calculate accurately individual thermal resistances of transistors in a given circuit.

Characterization of layout dependent thermal coupling in SOI CMOS current mirrors

A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 /spl mu/m SOI CMOS technology, with devices separated by as much as 20 /spl mu/m. Measurements were verified by electro-thermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.

Modelling of thin film SOI devices for circuit simulation including per-instance dynamic self-heating effects

Circuit simulation models for thin-film silicon-on-insulator (SOI) MOSFETs have been available for some time. However, these do not take account of the increasingly important self-heating effects that have been widely reported. These effects can lead to a significant reduction in the drain current resulting in negative differential resistance (NDR) in the I/V characteristics of SOI devices. Moreover, recent work has shown that thermal self-heating can also affect transient and small-signal behaviour. Here, we describe the implementation of a model in the SPICE3 code which has been developed to include thermal effects as well as some of the other common characteristics observed in SOI devices. Results of trial simulations are then presented.<<ETX>>

Measurement and simulation of self-heating in SOI CMOS analogue circuits

Summary form only given. The influence of dynamic self-heating on SOI MOSFET device behaviour is becoming well known. Although digital circuits typically operate sufficiently fast that self-heating does not affect behaviour, its effects must still be considered during parameter extraction. However, that the operation of analogue circuits will be influenced by self-heating is much more likely. Consequently, SPICE models should include self-heating, with accurately characterised thermal resistances and time constants. This paper explores the effect of self-heating on some common analogue circuits in a 0.7 /spl mu/m PD SOI technology, both from measurements and from SPICE simulations using a new SOI MOSFET model (STAG v2.0).

Characterisation of geometry dependence of SOI MOSFET thermal resistance and capacitance parameters

The study presented here provides valuable insight into the variation of thermal resistances and capacitances with SOI MOSFET device geometry. It demonstrates that small-signal measurements are a powerful technique for investigating heat flow paths in MOSFETs. An empirical approach is presented that allows estimation of dynamic thermal parameters directly from device geometries, based on a limited set of measurements.

Electrical measurement of silicon film and oxide thicknesses in partially depleted SOI technologies

Abstract This paper discusses the electrical measurement of silicon film, gate oxide and buried oxide thicknesses in partially depleted SOI CMOS technologies. For the first time a technique is presented that allows extraction of all three thicknesses, as well as the average silicon film doping concentration, using static threshold voltage measurements only. All measurements and extraction procedures can easily be fully automated, making this method suitable for both accurate parameter extraction and process control. The results obtained with this new technique have been verified by SEM cross-section measurement and a comparison is made with other electrical techniques.