C.F. Edwards

The effect of body contact series resistance on SOI CMOS amplifier stages

This paper examines some implications for analogue design of using body ties as a solution to the problem of floating body effects in partially-depleted (PD) SOI technologies. Measurements on H-gate body-tied structures in a 0.7-/spl mu/m SOI process indicate body-tie series resistances increasing into the M/spl Omega/ region. Both circuit simulation and measurement results reveal a delayed but sharper kink effect as this resistance increases. The consequences of this effect are shown in the context of a simple amplifier configuration, resulting in severe bias-dependent degradation in the small signal gain characteristics as the body-tie resistance enters the M/spl Omega/ region. It is deduced that imperfectly body tied devices may be worse for analogue design than using no body-tie at all.

Analogue design issues for SOI CMOS

There are many issues facing the analogue designer for mainstream VLSI SOI CMOS. Some are improvements (more useable bandwidth, less crosstalk), but many are difficulties. Thermal behaviour does not depend very strongly on the technology roadmap but possible matching problems do. The presence and degree of floating body behaviour hinges on specific process architecture as well as device layout. Except for kink effect coincident with saturation, most of these factors can be largely accommodated in design provided that the circuit level models and their extracted parameters are adequate. Without these, design becomes uncertain and requires time-consuming iterations incompatible with modern practices.

Measurement of buried oxide thermal conductivity for accurate electrothermal simulation of SOI device

Finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on insulator (SOI) devices. There is uncertainty about the conductivity of different forms of SiO/sub 2/, particularly that of buried oxides. This paper presents a novel approach to measure this conductivity, using structures that are compatible with standard bipolar or CMOS processes. Thermal conductivity values of 0.66 and 0.82 W/mK, respectively, were found for 300-nm BESOI and 420-nm SIMOX oxides at room temperature. The measured variations of thermal conducitivity with temperature agree well with bulk SiO/sub 2/ behavior. Better agreement between measurement and finite element simulation of MOSFET thermal resistance is obtained by using these extracted thermal conductivity values. It is also shown that the role of the silicon substrate in determining the thermal resistance of the device can be calculated using a simple analytical model. This is important when one wishes to calculate accurately individual thermal resistances of transistors in a given circuit.

A multibit /spl Sigma//spl Delta/ modulator in floating-body SOS/SOI CMOS for extreme radiation environments

This paper presents the design of an experimental first-order /spl Sigma//spl Delta/ modulator with 4-bit internal quantization, fabricated in a 1.5-/spl mu/m space-qualified radiation-hard partially depleted silicon-on-sapphire (SOS) digital CMOS process. This converter architecture has been chosen partly to allow investigation into the design of a range of common analog functions with two key issues in mind: one of technology and one environmental. First, both the architecture and the circuit design are optimized using a variety of unconventional techniques to account for the influence of extreme bias-dependent, radiation-induced threshold-voltage shifts of up to 1 V, as well as poor 1/f device noise. Second, the circuitry is specially adapted to accommodate the floating-body behavior of this type of process, wherein drain conductance varies considerably with drain bias and frequency. The design techniques are directly applicable to very large-scale-integration silicon-on-insulator (SOI) design, where similar device physics are encountered. Notwithstanding the severe constraints on the design, the fabricated circuit provides 9.7 bits of dynamic range in a 63-kHz signal bandwidth, only degrading to 9.1 bits after 23 Mrad(Si) of total dose /spl gamma/ radiation.

Measurement and simulation of self-heating in SOI CMOS analogue circuits

Summary form only given. The influence of dynamic self-heating on SOI MOSFET device behaviour is becoming well known. Although digital circuits typically operate sufficiently fast that self-heating does not affect behaviour, its effects must still be considered during parameter extraction. However, that the operation of analogue circuits will be influenced by self-heating is much more likely. Consequently, SPICE models should include self-heating, with accurately characterised thermal resistances and time constants. This paper explores the effect of self-heating on some common analogue circuits in a 0.7 /spl mu/m PD SOI technology, both from measurements and from SPICE simulations using a new SOI MOSFET model (STAG v2.0).

A high speed offset-compensated differential comparator in floating body CMOS SOS technology for radiation hard switched-capacitor systems

In this paper we describe how a high performance analogue cell has been designed and simulated using a SOS SPICE model, and successfully fabricated in a 1.5 /spl mu/m floating body SOS technology. The cell described here is a clocked comparator; this is a fundamental building block for realising high performance analogue-to-digital conversion in any technology. To achieve high tolerance to floating body effects, as well as radiation-induced bias and offset degradation, it is necessary to adopt highly specific design techniques to ensure performance is delivered.

Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

Starting from the basis that device matching is central to most analogue designs, the effects of static and dynamic signal history dependence on post-radiation device characteristics and analogue circuit cell performance are examined. The effects of unbalanced static and dynamic bias signals on matched devices subject to radiation is studied. Behavioural models for comparator cells and complete analogue to digital (A/D) converters are developed to assess the impact at cell and system level. New circuit design techniques are used too in the implementation of a 7-bit flash A/D converter fabricated in 1.5 /spl mu/m SOI/SOS CMOS; and measurements confirm that performance remains consistent up to very high dose levels.

A multi–bit ΣΔ modulator in floating body silicon–on–sapphire CMOS technology for extreme radiation environments

This paper presents the design of a first order ΣΔ modulator with 4-bit internal qunatisation, fabricated in a 1.5µm radiation hard partially depleted silicon-on-sapphire digital CMOS process. Both the architecture and the circuit design are optimised using a variety of unconventional techniques to account for the influence of extreme bias-dependent radiation induced threshold voltage shifts of up to 1V, as well as poor 1/f device noise. In addition, the circuitry is specially adapted to accommodate the floating body behaviour of this type of process, wherein drain conductance varies considerably with drain bias and frequency. These techniques are directly applicable to VLSI SOI design, where similar device physics are encountered. The circuit provides 9.7 bits of dynamic range in a 63kHz signal bandwidth, only degrading to 9.1 bits after 23Mrad(Si) of total dose γ radiation.