B. Mesman

Predictable Embedded Multiprocessor System Design

Consumers have high expectations about the video and audio quality delivered by media processing devices like TV-sets, DVD-players and digital radios. Predictable heterogenous application domain specific multiprocessor systems, which are designed around a networks-on-chip, can meet demanding performance, flexibility and power-efficiency requirements as well as stringent timing requirements. The timing requirements can be guaranteed by making use of resource management techniques and the analytical techniques that are described in this paper.

Dataflow analysis for real-time embedded multiprocessor system design

Dataflow analysis techniques are key to reduce the number of design iterations and shorten the design time of real-time embedded network based multiprocessor systems that process data streams. With these analysis techniques the worst-case end-to-end temporal behavior of hard real-time applications can be derived from a dataflow model in which computation, communication and arbitration is modeled. For soft real-time applications these static dataflow analysis techniques are combined with simulation of the dataflow model to test statistical assertions about their temporal behavior. The simulation results in combination with properties of the dataflow model are used to derive the sensitivity of design parameters and to estimate parameters like the capacity of data buffers.

Constraint analysis for DSP code generation

Code generation methods for digital signal processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of resource and timing constraints. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low register requirements.

Efficient scheduling of DSP code on processors with distributed register files

Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in the paper analyses the combination of limited register file capacity, resource- and timing constraints during scheduling. Value lifetimes are serialized until all capacity constraints are guaranteed to be satisfied after scheduling. Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for innermost loops of DSP algorithms.

Static resource models of instruction sets

Due to an increasing need for flexibility, embedded systems embody more and more programmable processors as their core components. Because of silicon area and power considerations, the corresponding instruction sets are often highly encoded to minimize code size for given performance requirements. This has hampered the development of robust optimizing compilers because the resulting irregular instruction set architectures are far from convenient compiler targets. Among others, they introduce a strong phase coupling between the tasks of instruction selection and scheduling. Traditional methods perform these tasks in different phases, thereby yielding inferior schedules. The authors present an approach that reduces the need for explicit instruction selection by transferring constraints implied by the instruction set to static resource constraints. All resulting schedules are then guaranteed to correspond to a valid implementation with available instructions. We demonstrate a practical way to identify and construct a static resource model from a given instruction set. Experimental results show the efficacy of our approach.

Limited Address Range Architecture for Reducing Code Size in Embedded Processors

In embedded systems a processor core must be designed with low power consumption, low cost and small silicon area in mind since program code often resides in on-chip ROM. To obtain small code size, not only the amount of instruction-level parallelism can be restricted by instruction sets, but also the encoding cost can be reduced by restricting the access to register files. However, communication among register files has to be supported by hardware, e.g. buses and wires, and compilers. In this paper, we propose a new type of architecture by limiting the encoding range to a subset of registers in a register file on the one hand, and keeping the overlap among different ranges on the other hand in order to support communication between all the functional units. We also propose the annotated conflict graph approach for modeling the range constraints in this architecture, which can be applied in combination with any scheduler. However, to overcome the phase coupling between address range assignment and scheduling in code generation, in this paper the address range constraints are transformed and integrated with the existing timing, resource and register file constraints. Constraint analysis techniques [9] are adapted to prune the search spaces based on those constraints. Results show that we can reduce code size up to 24.58% by applying our technique.

Constraint satisfaction for relative location assignment and scheduling

Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor implies resource constraints. Instead of random-access registers, relative location storages or rotating register files are used to exploit the available parallelism of resources by means of reducing the initiation interval in pipelined schedules. Therefore, the compiler or synthesis tool must deal with the difficult tasks of scheduling of operations and location assignment of values while respecting all the constraints including the storage file capacity. This paper presents a method that handles constraints of relative location storages during scheduling together with timing and resource constraints. The characteristics of the coloring of conflict graphs, representing the relative overlap of value instances, are analyzed in order to identify the bottlenecks for location assignment with the aim of serializing their lifetimes. This is done with pairs of loop instances of values until it can be guaranteed that all constraints will be satisfied.