C.A.J. van Eijk

Exploiting functional dependencies in finite state machine verification

This paper proposes a novel verification method for finite state machines (FSMs), which automatically exploits the relation between the state encodings of the FSMs under consideration. It is based on the detection and utilization of functionally dependent state variables. This significantly extends the ability of the verification method to handle FSMs with similar state encodings. The effectiveness of the proposed method is illustrated by experimental results on well-known benchmarks.

Exploiting Structural Similarities in a BDD-Based Verification Method

A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of dynamic variable ordering techniques already makes these tools more robust; a designer no longer needs to worry about a good initial variable order. In addition, we present a novel approach combining BDDs with a technique that exploits structural similarities of the circuits under comparison. We explain how these similarities can be detected and put to effective use in the verification process. Benchmark results show that the proposed method significantly extends the range of circuits that can be verified using BDDs.

A code-motion pruning technique for global scheduling

In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditionals in the behavioral description represents an obstacle to exploit parallelism. Most existing methods use greedy choices in such a way that the search space is limited by the applied heuristics. For example, they might miss opportunities to optimize across basic block boundaries when treating conditional execution. We propose a constructive method which allows generalized code motions. Scheduling and code motion are encoded in the form of a unified resource-constrained optimization problem. In our approach many alternative solutions are constructed and explored by a search algorithm, while optimal solutions are kept in the search space. Our method can cope with issues like speculative execution and code such duplication. Moreover, it can tackle constraints imposed by the advance choice of a controller, such as pipelined-control delay and limited branch capabilities. The underlying timing models support chaining and multicycling. As tasking code motion into account may lead to a larger search space, a code-motion pruning technique is presented. This pruning is proven to keep optimal solutions in the search space for cost functions in terms of schedule lengths.

Identification and exploitation of symmetries in DSP algorithms

In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit these symmetries. However current hardware and software compilers show deficiencies, because they cannot identify them. In this paper, we propose two techniques to automatically detect and utilize symmetry. Both techniques introduce sequence edges between operations such that the feasibility of the scheduling problem is preserved, while the symmetry is broken. In combination with existing techniques for constraint analysis, this enhances the quality of compilers considerably, as is shown by benchmark results.

An efficient divide and conquer algorithm for exact hazard free logic minimization

In this paper we introduce the first divide and conquer algorithm that is capable of exact hazard-free logic minimization in a constructive way. We compare our algorithm with the method of Dill and Nowick (1992), which was the only known method for exact hazard-free minimization. We show that our algorithm is much faster than the method proposed by Dill and Nowick by avoiding a significant part of the search space. We argue that the proposed algorithm is a promising framework for the development of efficient heuristic algorithms.

A constructive method for exploiting code motion

In this paper we address a resource-constrained optimization problem for behavioral descriptions containing conditionals. In high-level synthesis of ASICs or in code generation for ASIPs, most methods use greedy choices in such a way that the search space is limited by the applied heuristics. For example, they might miss opportunities to optimize across basic block boundaries when treating conditional execution. We propose an approach based on local search and present a constructive method to allow unrestricted types of code motion, while keeping optimal solutions in the search space. A code-motion pruning technique is presented for cost functions optimizing schedule lengths. A technique for treating concurrent flows of execution is also described.

Register Binding for Predicated Execution in DSP Applications

Predicated execution is an efficient mechanism to avoid conditional constructs in application programs. In this paper we describe how an existing method for register binding can be extended to support predicated execution. The method exploits the combination of register constraints, resource and timing constraints and models the overlap of value lifetimes in a conflict graph. In our extension, mutually exclusive values are identified and are used for reconstructing the conflict graph. Register binding for predicated execution in case of software pipelining is also addressed in this paper. Experiments in the Facts environment show that the register pressure is greatly reduced with this technique.

Run-time consistency checking in discrete simulation models

A new and efficient method is presented to improve the validation capabilities of a discrete event simulator. Discrete event monitors are introduced as a means to analyse event traces during a simulation run. This facilitates the defection and location of erroneous behaviour in a design specification. Furthermore, a specification language for discrete event monitors is described and it is shown how this language facilitates the integration of other specification methods. Experimental results are presented to demonstrate the efficiency of the proposed techniques.<<ETX>>

Constraint satisfaction for storage files with Fifos or stacks during scheduling

This paper presents a method that, during scheduling of DSP algorithms, handles constraints of storage files with FIFOs or stacks together with resource and timing constraints. Constraint analysis techniques and the characteristics of the exact coloring of conflict graphs are used to identify values that are bottlenecks for storage assignment with the aim of ordering their accesses. This is done with pairs of values until it can guarantee that all constraints will be satisfied.