B. Rajasekharan

The Charge Plasma P-N Diode

A simulation study on a new rectifier concept is presented. This device basically consists of two gates with different workfunctions on top of a thin intrinsic or lowly doped silicon body. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e., a charge plasma p-n diode is formed in which no doping is required. Simulation results reveal a good rectifying behavior for well-chosen gate workfunctions and device dimensions. This concept could be applied for other semiconductor devices and materials as well in which doping is an issue.

Fabrication and Characterization of the Charge-Plasma Diode

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

Dimensional scaling effects on transport properties of ultrathin body p-i-n diodes

Device scaling has been a subject of research for both optoelectronics and electronics. In order to investigate the electronic properties of scaled devices we studied lateral p-i-n structures using thin silicon on insulator (SOI) or poly-Si layers of varying dimension. With the help of these structures we try to explain the size dependencies on electronic transport properties. Further, we also propose a new device concept called charge plasma diode.

On the modelling and optimisation of a novel Schottky based silicon rectifier

The charge plasma (CP) diode is a novel silicon rectifier using Schottky barriers, to circumvent the requirement for doping and related problems when small device dimensions are used. We present a model for the DC current voltage characteristics and verify this using device simulations. The model revealed an exponential dependence of the current on the metal work functions. And approximate linear dependence on the device geometry. The model is used to optimise the device performance. We show a factor 30 improvement in on/off current ratio (and hence rectification) toward 10E7 by appropriate sizing of the lateral device dimensions at given specific metal work functions.

Electrostatic Doping in Semiconductor Devices

To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.