Erik Jouwert Faber

On the kinetics of platinum silicide formation

In this work, the kinetics of platinum silicide formation for thin Pt films (50 nm) on monocrystalline silicon is investigated via in situ resistance measurements under isothermal (197–275 °C) conditions. For Pt2Si diffusion limited growth was observed. For PtSi formation, however, no linear relation between silicide thickness and t was found. PtSi growth over time could be described using the Avrami relation rendering Avrami exponent n=1.4±0.1. Additionally, an effective activation energy EA=1.7±0.1 eV was derived using the Avrami k values. The findings are important for obtaining well defined silicide films and silicide-to-silicon contacts.

Novel Test Structures for Dedicated Temperature Budget Determination

We present a novel method for determining the temperature budget of the process side of silicon substrates and chips, based on well-known silicide formation reactions of metal-Si systems and (four-point probe) resistance measurements. In this paper, we focus on the Pd-Si system that is most temperature sensitive in the range from 100°C to 200°C. A variety of test structures is introduced to exploit the specific properties of the diffusion-limited reaction between Pd and Si. Among others, this resulted in gap-based layouts that facilitate an extension of the temperature range to 350°C. Designs and measurement results are presented, indicating the practicality and the robustness of the proposed technique.

Novel test structures for temperature budget determination during wafer processing

Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100 – 200 °C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.

Gap-closing test structures for temperature budget determination

We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.