Jurriaan Schmitz

RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

Test structure design considerations for RF-CV measurements on leaky dielectrics

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

Comparison of soft-breakdown triggers for large-area capacitors under constant voltage stress

This work quantitatively compares soft breakdown identification methods for constant voltage stress of large-area nMOS capacitors (up to 10 mm/sup 2/) with 1.8- to 12-nm gate-oxide thickness (with negative gate voltage). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation. We present a method to quantify the system background noise, and show results of data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.

Channel profile engineering of 0.1 /spl mu/m-Si MOSFETs by through-the-gate implantation

A novel approach to the super-steep retrograde (SSR) channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in place (TGi). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

Soft breakdown triggers for large area capacitors under constant voltage stress

This work quantitatively compares breakdown triggers for constant voltage stress of large area NMOS capacitors (up to 10 mm/sup 2/) with 1.8 to 12 nm gate oxide thickness (with negative V/sub G/). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation (RMS). We also present data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.

Dopant profile engineering of advanced Si MOSFET’s using ion implantation

Abstract Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.

A study of measurement system noise for sensitive soft breakdown triggering

This work discusses a simple and effective method to determine the short-term repeatability of current measurements over a large range of currents. With this method, we obtain a quantitative estimate of the background fluctuations that obscure the soft breakdown signal of a large area MOS capacitor under constant voltage stress. Details of the fluctuations are discussed, as well as the consequences for soft breakdown detection.

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 /spl mu/m CMOS low-voltage applications

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to control threshold voltage V/sub T/, while short channel effects (SCE) were completely suppressed down to 100 nm gate lengths by heavily doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V/sub T/ roll-off behaviour, and 67 mV/dec sub-V/sub T/ voltage swing. The low channel doping leads to significant improvements in the channel mobility and parasitic capacitances, resulting in excellent I/sub on//I/sub off/ behaviour and record ring oscillator delays for low-voltage operation. Process variation analysis confirmed the high manufacturing potential for the approach suggested. The approach can be extended to n-type devices with a suitable choice of gate work function.

Channel formation for 0.15 /spl mu/m CMOS using through-the-gate implantation

Front-end optimization of a 0.15 /spl mu/m CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 /spl mu/m CMOS transistor and circuit performance was obtained.

Characterisation of low energy boron implants and electrical results of submicron PMOS transistors

Low energy boron implants between 200 eV and 10 keV have been characterised for the effect of channelling and of pre-amorphisation on the as-implanted profiles. Suitable rapid thermal anneal conditions for a shallow drain formation compatible with a 0.18 /spl mu/m CMOS process were determined. One of these conditions was then used to fabricate PMOS transistors with shallow drain extensions using a 0.18 /spl mu/m flow chart. Transistor characteristics such as threshold voltage, junction leakage and asymmetry were then measured as a function of implanted species and energy, and of gate length.