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Dive into the research topics where B. Tasic is active.

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Featured researches published by B. Tasic.


international test conference | 2011

Defect Oriented Testing for analog/mixed-signal devices

Bram Kruseman; B. Tasic; Camelia Hora; Jj Dohmen; Hamidreza Hashempour; Maikel van Beurden; Yizi Xing

We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup of over 100x in the DOT process. Moreover, a number of methods are presented to improve the accuracy of this algorithm. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the analyzed production tests of the device can be reduced by at least 50%.


design, automation, and test in europe | 2011

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hamidreza Hashempour; Jj Dohmen; B. Tasic; Bram Kruseman; Camelia Hora; Maikel van Beurden; Yizi Xing

We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.


IEEE Design & Test of Computers | 2012

Defect Oriented Testing for Analog/Mixed-Signal Designs

Bram Kruseman; B. Tasic; Camelia Hora; Jj Dohmen; Hamidreza Hashempour; M. van Beurden; Yizi Xing

In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.


International Journal of Computer Mathematics | 2007

Stability analysis of the BDF Slowest-first multirate methods

A. Verhoeven; E.J.W. ter Maten; R.M.M. Mattheij; B. Tasic

This paper deals with the stability analysis of BDF Slowest-first multirate time-integration methods applied to the transient analysis of circuit models. From an asymptotic analysis it appears that these methods are indeed stable if the subsystems are stable and weakly coupled.


CASA-report | 2007

Automatic partitioning for multirate methods

A. Verhoeven; B. Tasic; Theo G. J. Beelen; E.J.W. ter Maten; Rmm Mattheij

The (nonlinear) transient analysis of electrical circuit models plays an important role in circuit design. Multirate time integration can be able to achieve the same accuracy for much lower costs. An essential assumption is the existence of a good partition of the circuit in a slow and fast part. This paper describes how this can be done automatically.


design, automation, and test in europe | 2012

Advances in variation-aware modeling, verification, and testing of analog ICs

Dimitri De Jonghe; Elie Maricau; Georges Gielen; Trent McConaghy; B. Tasic; Haralampos-G. D. Stratigopoulos

This tutorial paper describes novel scalable, nonlinear/generic, and industrially-oriented approaches to perform variation-aware modeling, verification, fault simulation, and testing of analog/custom ICs. In the first section, Dimitri De Jonghe, Elie Maricau, and Georges Gielen present a new advance in extracting highly nonlinear, variation-aware behavioral models, through the use of data mining and a re-framing of the model-order reduction problem. In the next section, Trent McConaghy describes new statistical machine learning techniques that enable new classes of industrial EDA tools, which in turn are enabling designers to perform fast and accurate PVT / statistical / high-sigma design and verification. In the third section, Bratislav Tasić presents a novel industrially-oriented approach to analog fault simulation that also has applicability to variation-aware design. In the final section, Haralampos Stratigopoulos describes describes state-of-the-art analog testing approaches that address process variability.


Archive | 2018

Robust Optimization of an RFIC Isolation Problem Under Uncertainties

Piotr Putek; Rick Janssen; Jan Niehof; E. Jan W. ter Maten; Roland Pulch; Michael Günther; B. Tasic

Modern electronics systems involved in communication and identification impose demanding constraints on both reliability and robustness of components. On the one hand, it results from the influence of manufacturing tolerances within the continuous down-scaling process into the output characteristics of electronic devices. On the other hand, the increasing integration process of various systems on a single die force a circuit designer to make some trade-offs in preventing interference issues and in compensating coupling effects. Thus, constraints in terms of statistical moments have come in a natural way into optimization formulations of electronics products under uncertainties. Therefore, in this paper, for the careful assessment of the propagation of uncertainties through a model of a device a type of Stochastic Collocation Method (SCM) with Polynomial Chaos (PC) was used. In this way a response surface model can be included in a stochastic, constrained optimization problem. We have illustrated our methodology on a Radio Frequency Integrated Circuit (RFIC) isolation problem. Achieved results for the optimization confirmed efficiency and robustness of the proposed methodology.


European Consortium for Mathematics in Industry | 2016

Nanoelectronic Coupled Problem Solutions: Uncertainty Quantification of RFIC Interference

Piotr Putek; Rick Janssen; Jan Niehof; E. Jan W. ter Maten; Roland Pulch; B. Tasic; Michael Günther

Due to the key trends on the market of RF products, modern electronics systems involved in communication and identification sensing technology impose requiring constraints on both reliability and robustness of components. The increasing integration of various systems on a single die yields various on-chip coupling effects, which need to be investigated in the early design phases of Radio Frequency Integrated Circuit (RFIC) products. Influence of manufacturing tolerances within the continuous down-scaling process affects the output characteristics of electronic devices. Consequently, this results in a random formulation of a direct problem, whose solution leads to robust and reliable simulations of electronics products. Therein, the statistical information can be included by a response surface model, obtained by the Stochastic Collocation Method (SCM) with Polynomial Chaos (PC). In particular, special emphasis is given to both the means of the gradient of the output characteristics with respect to parameter variations and to the variance-based sensitivity, which allows for quantifying impact of particular parameters to the variance. We present results for the Uncertainty Quantification of an integrated RFCMOS transceiver design.


CASA-report | 2016

Fitting generalized Gaussian distributions for process capability index

T.G.J. Beelen; Jj Dohmen; E. Jan W. ter Maten; B. Tasic

The design process of integrated circuits (IC) aims at a high yield as well as a good IC-performance. The distribution of measured output variables will not be standard Gaussian anymore. In fact, the corresponding probability density function has a more flat shape than in case of standard Gaussian. In order to optimize the yield one needs a statistical model for the observed distribution. One of the promising approaches is to use the so-called Generalized Gaussian distribution function and to estimate its defining parameters. We propose a numerical fast and reliable method for computing these parameters.


European Consortium for Mathematics in Industry | 2015

Fast fault simulation to identify subcircuits involving faulty components

B. Tasic; Jj Dohmen; ter Ejw Jan Maten; Tgj Beelen; Hhjm Rick Janssen; Wha Wil Schilders; Michael Günther

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation we simulate all situations: new connections and each with different values for the newly added element. We also consider “opens” (broken connections). During the transient simulation the solution of a faulty circuit is compared to the golden solution of the fault-free circuit. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation in which the golden solution and all faulty solutions are calculated over a same time step. Finally, we store a database with detectable deviations for each fault. If such a detectable output “matches” a measurement result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault.

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A. Verhoeven

Eindhoven University of Technology

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R.M.M. Mattheij

Eindhoven University of Technology

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T.G.J. Beelen

Eindhoven University of Technology

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Roland Pulch

University of Greifswald

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E. Jan W. ter Maten

Eindhoven University of Technology

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