Bram Kruseman

On hazard-free patterns for fine-delay fault testing

This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.

Transient current testing of 0.25 /spl mu/m CMOS devices

Transient current testing (I/sub DDT/) has been often cited as an alternative and/or supplement to I/sub DDQ/ testing. The effectiveness of our I/sub DDT/ test method is compared with I/sub DDQ/ as well as with SA-based voltage testing for devices produced in 0.25 /spl mu/m technology. For these devices a large vector-to-vector spread in I/sub DDT/ is observed. This spread is investigated together with the die-to-die spread to determine a pass/fail criterion. The vector-to-vector spread is compensated by comparing the measured I/sub DDT/ values with those of a known good (golden) device. A hardware solution for an I/sub DDT/ monitor is presented which includes a correction for the golden device signature. Therefore real-time I/sub DDT/ testing on a digital tester without data-processing becomes feasible.

The future of delta I/sub DDQ/ testing

The increase in off-state current for deep submicron technologies will make conventional I/sub DDQ/ testing ineffective. An attractive alternative is differential I/sub DDQ/ or /spl Delta/I/sub DDQ/ testing as a function of the test pattern; it is relatively easy to implement it in a production environment and the method can detect I/sub DDQ/ anomalies of a few percent of the off-state current itself. In its simplest form the method is limited by state-dependent leakage current variations. More advanced versions of /spl Delta/I/sub DDQ/ testing can cope with these state-dependencies and are useful for off-state currents in the milliampere range. The presence of state-dependent leakage currents can be utilised to detect large passive defects, which are otherwise undetectable with /spl Delta/I/sub DDQ/. For even higher leak-age currents circuit-specific state-dependencies become the limiting factor and make /spl Delta/I/sub DDQ/ testing ineffective for devices with off-state currents above 100 mA.

Trends in testing integrated circuits

New process technologies, increased design complexity, and more stringent customer quality requirements drive the need for better test quality, improved test program development, and faster ramp-up at overall lower product cost. In this paper we describe the main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips.

On test conditions for the detection of open defects

The impact of test conditions on the detectability of open defects is investigated. We performed an inductive fault analysis on representative standard gates. The simulation results show that open-like defects result in a wide range of different voltage-delay dependencies, ranging from a strongly increasing to a strongly decreasing delay as a function of voltage. The behaviour is not only determined by the defect location but also by the test pattern. Knowing the expected behaviour of a certain defect location helps failure localisation. The detectability of a defect is strongly determined by the behaviour of the affected path as well as that of the longest path. Our simulations and measurements show that in general elevated supply voltages give a better detectability of open-like defects

Comparison of defect detection capabilities of current-based and voltage-based test methods

The industrial default to test random logic is based on stuck-at fault test patterns applied via scan-chains. This test-method can be described as static voltage testing. A second well-known method is I/sub DDQ/ resting, which can be described as static current testing. This second method is especially suited for detecting resistive shorts. For deep sub-micron technologies new defect mechanisms start to become important. Especially, opens are a much feared type of defect since static test methods are less suited to detect these defects. Dynamic test methods such as delay-fault testing and transient current testing could fill this gap in the test suite. The paper gives an overview of the aforementioned test-methods including some of the new current-based test methods necessary for deep submicron technologies and their defect detection capabilities.

Comparison of I/sub DDQ/ testing and very-low voltage testing

I/sub DDQ/ testing is a well-known test method to filter dies with reliability risks. However, the test method is endangered by the increase in off-state current in advanced process technologies. An alternative for detecting resistive shorts is very-low voltage (VLV) testing. This test method tests dies at a strongly reduced supply voltage. The smaller the supply voltage, the higher the sensitivity for defects. This paper investigates if VLV testing can replace I/sub DDQ/ testing. To obtain a significant increase in defect coverage, one must use a supply voltage below 2/spl times/V/sub T/. In the experiments, a supply voltage of 1.5/spl times/V/sub T/ was used with relaxed timing. This makes the method more than twice as sensitive compared to 2/spl times/V/sub T/ and allows one to detect shorts with resistance of five times the detection limit at the nominal supply voltage. However, even with these settings we were only capable of detecting a small fraction of the I/sub DDQ/ anomalies. Therefore VLV is not suited to replace I/sub DDQ/ testing.

Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs

Soft error rate is an important reliability issue in deep-submicron IC design. Crucial is the impact of technology scaling on the critical charges of SRAM cells and flip-flops. In the present work, this scaling is studied using both circuit simulation and accelerated SER measurement.

Detection of resistive shorts in deep sub-micron technologies

Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for the detection of resistive shorts. The main limitation of ∆IDDQ testing is the intra-die variation of the threshold voltage which results in variations in the off-state current. Two methods are investigated that improve the detection capabilities of ∆IDDQ testing. The first method reduces the impact of intra-die variation by reducing the amount of logic that switches states. This method can handle very large off-state currents although at the cost of a substantial increase in test time. The second method investigates the correct scaling of the intra-die variations as a function of temperature. We show that both methods improve the detection capabilities of ∆IDDQ testing.