Jj Dohmen

Defect Oriented Testing for analog/mixed-signal devices

We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup of over 100x in the DOT process. Moreover, a number of methods are presented to improve the accuracy of this algorithm. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the analyzed production tests of the device can be reduced by at least 50%.

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

Defect Oriented Testing for Analog/Mixed-Signal Designs

In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.

Fitting generalized Gaussian distributions for process capability index

The design process of integrated circuits (IC) aims at a high yield as well as a good IC-performance. The distribution of measured output variables will not be standard Gaussian anymore. In fact, the corresponding probability density function has a more flat shape than in case of standard Gaussian. In order to optimize the yield one needs a statistical model for the observed distribution. One of the promising approaches is to use the so-called Generalized Gaussian distribution function and to estimate its defining parameters. We propose a numerical fast and reliable method for computing these parameters.

Fast fault simulation to identify subcircuits involving faulty components

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation we simulate all situations: new connections and each with different values for the newly added element. We also consider “opens” (broken connections). During the transient simulation the solution of a faulty circuit is compared to the golden solution of the fault-free circuit. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation in which the golden solution and all faulty solutions are calculated over a same time step. Finally, we store a database with detectable deviations for each fault. If such a detectable output “matches” a measurement result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault.

Terminal current interpolation for multirate time integration of hierarchical IC models

Multirate time-integration methods [3–5] appear to be attractive for initial value problems for DAEs with latency or multirate behaviour. Latency means that parts of the circuit are constant or slowly time-varying during a certain time interval, while multirate behaviour means that some variables are slowly time-varying compared to other variables. In both cases, it would be attractive to integrate these slow parts with a larger timestep than the other parts. This saves the computational workload while the accuracy is preserved. A nice property of multirate is that it does not use any linear structure, in contrast to MOR, but only a relaxation concept. If the coupling is sufficiently monitored and the partitioning is well chosen, multirate can be very efficient.