Bah-Hwee Gwee

A GA paradigm for learning fuzzy rules

Abstract In this paper, we describe a paradigm for learning fuzzy rules using genetic algorithms (GA). We formulate our problem of learning as follows: given a set of linguistic values that characterize the input and output state variables of the system in consideration, derive an n -rule fuzzy control algorithm. The value n represents a specified constraint of the GA in searching for a functional ruleset. The GA learning paradigm is powerful since it requires no prior knowledge about the systems behavior in order to formulate a set of functional control rules through adaptive learning. We present our simulation results using the classical inverted pendulum control problem to demonstrate the effectiveness of the GA learning scheme. Results have shown that the approach has great potential as a tool for the learning of fuzzy control rules, particularly in situations where the knowledge from a human expert is not easily accessible.

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator

A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) /spl ap/0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial /spl sim/47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (/spl sim/60 /spl mu/W @1.1 V and 48-kHz sampling rate, and THD /spl ap/0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids.

A micropower low-distortion digital pulsewidth modulator for a digital class D amplifier

We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument class D amplifier. The PWM embodies a novel delta-compensation (/spl delta/C) sampling process and a novel pulse generator. The /spl delta/C process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion (THD). Its arithmetic computation is however, substantially simplified. We analytically derive the double Fourier series expression for the /spl delta/C process and show that the THD is low. The pulse generator is based on a hybrid 9-b counter 3-b tapped-delay-line. We investigate the compromise between the different design parameters that affect its power dissipation and THD. The complete proposed PWM features a simple circuit implementation (small IC area), micropower low voltage operation (/spl sim/22.1 /spl mu/W at 1.1 V), low sampling rate (48 kHz) and low harmonic distortion (/spl sim/0.2%), thereby rendering it suitable for a practical digital hearing instrument. We verify our design by means of computer simulations and on the basis of experimental measurements.

A micropower low-voltage multiplier with reduced spurious switching

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ~5.6 and ~10 per adder in the adder block in conventional 16times16-bit and 32times32-bit designs respectively to ~2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16times16-bit design dissipates ~32% less power, is ~20% slower but has ~20% better energy-delay-product (EDP) than conventional 16times16-bit multipliers. Our 32times32-bit design is estimated to dissipate ~53% less power, ~29% slower but is ~39% better EDP than the conventional general multiplier

An investigation into the parameters affecting total harmonic distortion in low-voltage low-power Class-D amplifiers

We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the output stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the output stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.

A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids

We describe a 16-channel critical-like spaced, high stopband attenuation (ges60 dB, 109thtimes16-order), micropower (247.5 muW@1.1 V, 0.96 MHz), small integrated circuit (IC) area (1.62 mm2@0.35-mum CMOS) finite impulse response filter bank core for power-critical hearing aids. We achieve the low-power and small IC area attributes by our proposed common pre-computational unit to generate a set of pre-calculated intermediate values that is shared by all 16 channels. We also take advantage of the consecutive zeros in the coefficients of the filter channels, allowing the multiplexers therein to be simplified. We show that our design is very competitive compared to reported designs, and with the advantages of higher stopband attenuation and linear phase frequency response. Compared to a design using the usual approach, our design features 47% lower power dissipation and 37% smaller IC area

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features ~37% lower energy per FFT/IFFT computation than the sync approach but with ~10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35-mum CMOS process) can be operated at 1.0 V and dissipates 93 nJ.

A GA with heuristic-based decoder for IC floorplanning

In this paper, we describe a genetic algorithm with heuristic-based layout decoder (GAHD) for floorplanning in IC design. The basic idea is to make use of a GA to search for an optimal arrangement of circuit modules on a pre-specified layout area. To achieve a GA that is efficient in floorplanning, we employ a technique to systematically determine suitable weighting coefficients of the search objectives in deriving a suitable objective function. For each arrangement of flexible modules derived by the GA, the aspect ratios of all the modules are fixed such that the modules when fully placed and routed will yield a floorplan that is efficient in terms of area and wirelength. For this purpose, we designed a heuristic-based layout decoder for determining the optimal aspect ratio and orientation of each module. Our results show improvement over other reported floorplanning algorithms based on simulations of the AMI33 benchmark problem.

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal VDD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery (VDD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at VDD = 1.2 V, it dissipates 186 μW.

Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different types of gating configurations using only PMOS transistor (PMOS Gating), only NMOS transistor (NMOS Gating), and both types of transistors (Dual Gating) are examined and compared. The effectiveness of the proposed power gating technique to the Combinational Block therein with different data input rates is investigated. Based on the computer simulation results, we have found that ≫70% wasted power reduction (including both short-circuit and leakage powers) as compared to the conventional asynchronous-logic pipeline stage can be achieved with all gating configurations. In particular, Dual Gating achieves the best wasted power reduction of 86% for short-circuit power and 99% for leakage power @ 10Mbps input rate.