Victor Adrian

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator

A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) /spl ap/0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial /spl sim/47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (/spl sim/60 /spl mu/W @1.1 V and 48-kHz sampling rate, and THD /spl ap/0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids.

A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC–DC Converters

We present a novel randomized wrapped-around pulse position modulation (RWAPPM) scheme for digital modulators of dc-dc converters. Unlike the reported modulation schemes that require a varying switching period (thereby resulting in high attenuation or complete elimination of discrete harmonics), the proposed RWAPPM conversely requires only a constant switching period (thereby advantageous in terms of easy realization in hardware), and yet, its discrete harmonics are negligible. We derive an expression for the spectrum of the RWAPPM scheme to analytically obtain the peak spectral power and ripple noise voltage of RWAPPM. This expression further provides insight to the parameters that influence the RWAPPM spectrum. We benchmark the RWAPPM scheme against the ubiquitous conventional pulsewidth modulation scheme and six reported (randomized and frequency modulation) schemes. The RWAPPM scheme features negligible discrete harmonics [≤ -158 dB relative to full scale (dBFS)], and among the modulation schemes, it features the lowest peak spectral power at -26.6 dBFS (before low-pass filtering) and relatively low ripple noise at 2 mVrms (after low-pass filtering) for a 3.6-2.5-V conversion and an effective switching frequency of 120 kHz. We verify the derived expression and attributes of the RWAPPM spectrum by computer simulations and on the basis of experimental measurements on a dc-dc converter.

A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids

We present a micropower digital modulator for class-D amplifiers for power-critical digital hearing aids. The modulator design embodies a proposed Lagrange interpolation (a combined first- and second-order Lagrange) algorithmic pulsewidth modulation (PWM) and a third-order DeltaSigma noise shaper. By means of double-Fourier-series analysis, we analyze and determine the harmonic nonlinearities of the proposed algorithmic PWM. At 48-kHz sampling, 96-kHz PWM output, 997-Hz input, and input modulation index=0.9, the modulator circuit achieves a total harmonic distortion+noise &nbsp;(<i>THD</i>+<i>N</i>) of - 74&nbsp;dB (0.02%) over an 8-kHz voice bandwidth-a 12-dB <i>THD</i>+<i>N</i> improvement over a reported design and yet dissipates only ~ 50% of the power. The proposed modulator dissipates the lowest power dissipation of all modulators compared, and by means of a proposed figure of merit, the proposed modulator exhibits very competitive performance. The modulator IC is fabricated in a 0.35-mum digital CMOS process with a core area of 0.46 mm².

A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers

We propose a novel Direct Interpolation (DI) sampling process and novel hybrid pulse generator for a Pulse Width Modulator (PWM) for a digital Class D amplifier. The DI sampling process features the lowest harmonic distortion compared to other algorithmic sampling processes. The computation for the DI process is simple, leading to small IC area and very low power dissipation (7 /spl mu/W@1.1 V). We analytically derive the double Fourier expression for the DI process and show that the THD is very low (<0.03%). The novel hybrid pulse generator embodies a counter, noise shaper, and novel 1-bit frequency doubler. The complete PWM features a simple circuit implementation (small IC area), micropower low voltage operation (/spl sim/60 /spl mu/W@1.1 V), low sampling rate (48 kHz) and low harmonic distortion (/spl sim/0.03%).

A Review of Design Methods for Digital Modulators

One of the main components in a digital class D amplifier is the digital modulator. This modulator is necessary so that an N-bit digital input can be converted into 1-bit modulated pulses, which in turn are used for high efficiency operation in the output stage of the class D amplifier. In this paper, we review three design methods for digital modulators. The three design methods are: pulse width modulation, pulse density modulation, and algorithmic PWM-multi-bit DeltaSigma modulation. Among these methods, the algorithmic PM-multi-bit DeltaSigma modulation can have the best trade-offs between performance and power dissipation.

Design of a 5 GS/s fully-digital digital-to-analog converter

We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce the clock speed from 10 GHz to 625 MHz. The lower clock speed allows the use of standard cells for designing the digital computational circuits of the FD DAC. The critical building blocks of the FD DAC are laid-out in a 65 nm CMOS process. The post-layout simulation results show that the Signal to Noise and Distortion Ratio and the in-band Spurious-Free Dynamic Range of the output signal are 36 dB and 44 dBc respectively.

A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier

In this paper, we propose a sampling process for low voltage (1.1V) power-critical low-distortion digital class D amplifiers. The sampling process combines first and second-order Lagrange interpolation techniques to effectively increase the sampling rate without the usual overheads. The computation is also simple. The complete class D amplifier features a very low power dissipation (58.8/spl mu/W), low total harmonic distortion (-85.6dB FS) and high signal-to-noise ratio (99dB FS). The power saving is /spl sim/21% and the THD is improved by 9.8dB FS compared to a design embodying only a first order sampling process. We also provide an analysis of the power dissipation of the load power.

Design of a variable-delay window ADC for switched-mode DC-DC converters

We propose a novel Variable-Delay Window ADC (VDWADC) design for digitally-controlled switched-mode dc-dc converters. In conventional Window ADCs based on the voltage-controlled delay line, the input voltage supplies the delay line. Thus, the conversion speed slows down when the input voltage decreases. The VDWADC is based on delay lines whose supply voltages are independent of the supply voltage. Hence, when the input voltage decreases, the conversion speed does not slow down. The VDWADC is simulated using 180 nm CMOS process and a supply voltage of 1.8 V. It achieves a quantization step of 0.05 V, or equivalently, a resolution of ~5.2 bits.

A hybrid modulation scheme for digital Class D amplifier modulators

In this paper, we adopt a hybrid modulation scheme for digital modulators of Class D amplifiers of power-critical digital hearing aids. The hybrid modulation scheme comprises the Delta-Sigma modulation (ΔΣM) scheme and the Pulse Width Modulation (PWM) scheme. The ΔΣM of the hybrid modulation scheme quantizes down the input data while the PWM generates 3-state output pulses corresponding to the quantized data. For this hybrid modulation scheme, we propose to quantize down the input to an output with 5 quantization levels. By using this amount of quantization levels, it is possible to obtain higher output linearity than that obtained by using the ΔΣM alone (same 3-state, but only 3 quantization levels). It is also possible to generate the output pulses without using a higher clock frequency than the input sampling frequency - unlike the usual PWM pulse generation that typically requires higher clock frequency. We also propose a simple pulse randomizer to improve the output linearity. We simulate a digital modulator design embodying the hybrid modulation scheme and the pulse randomizer, and compare its performance with that of a similar design employing a 3-state ΔΣM scheme alone. The THD+N of the output from the hybrid scheme modulator is −85 dB and is 10 dB better than that of the ΔΣM modulator.

Spectral Analysis of Randomized Switching Frequency Modulation Scheme with a Triangular Distribution for DC-DC Converters

Randomized modulation schemes are often employed in dc-dc converters to reduce the magnitude of discrete harmonics in the output spectrum. One of these schemes is Randomized Switching Frequency modulation (RSFM) that completely eliminates the discrete harmonics by randomizing its switching period (switching frequency) to follow a uniform distribution. In this paper, we investigate RSFM with its switching period following a triangular distribution. We show that RSFM with a triangular distribution is as effective as RSFM with a uniform distribution in eliminating the discrete harmonics, and has a slightly better (1 dB) reduction in the peak spectral power of a standard modulation scheme and a better (~2.5 dB) ripple noise voltage (at 12 V to 5 V conversion and 10 microseconds average switching period).