Pranav Kumar Asthana

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT=2 nm) and dielectric, HfO2 at VGS=1 V and temperature of 300 K have ION of 0.02-12.5 mA/μm, ION/IOFF of 105-1012, and subthreshold swing (average) of 16-74 mV/decade.

Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V semiconductor compound, indium aluminium arsenide. The analog performance parameters are extracted using device simulations and also compared with the Si JLTFET. We show that III–V JLTFET delivers much better performance parameters, in comparison to Si JLTFET, which includes transconductance generation efficiency (Gm/ID), intrinsic gain (GmRo) and unity gain frequency (fT) along with various gate capacitances.

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor (TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, Gm, output conductance, GD, and C–V characteristics of our proposed device. Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in ION of ∼0.23 mA μm−1, IOFF of ∼2.2 × 10−17 A μm−1, ION/IOFF of ∼1013, sub-threshold slope (SS) of ∼12 mV dec−1, DIBL of ∼93 mV V−1 and Vth of ≃0.11 V at room temperature and VDD of 0.7 V. This indicates that the H-JLTFET can play an important role in the further development of low power switching applications.

High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

We present a GaSb/InAs junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology. Numerical simulations resulted in an IOFF of ~8 × 10−17 A/μm, ION of ~9 μA/μm, ION/IOFF of ~1 × 1011, subthreshold slope of 9.33 mV/dec and DIBL of ~87 mV/V for GaSb/InAs JLTFET at a temperature of 300 K, gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.

Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction engineering is done to optimize the position of the Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in doping, gate work function, the mole fraction of SiGe and the dielectric constant. Comparison of the optimized, heterostructured silicon channel using numerical simulations indicates that ION increases from 0.12 to 15 μA μm−1, ION/IOFF increases from 4 × 106 to 3 × 109, and the subthreshold slope decreases from 80 to 43 mV dec−1 for a 22 nm channel with a supply voltage of 0.7 V.

Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor

We propose a dynamic threshold voltage junctionless tunnel FET (DT-JLTFET) in which the threshold voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate. The impact of the threshold voltage shift on the overall performance of the device is also studied. A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Si0.7Ge0.3 source JLTFET.

Junctionless Tunnel Field Effect Transistor with Nonuniform Doping

In this paper, the dc performance of a double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been further enhanced with the implementation of double sided nonuniform Gaussian doping in the channel. The device has been simulated for different channel materials such as Si and various III-V compounds like Gallium Arsenide, Aluminium Indium Arsenide and Aluminium Indium Antimonide. It is shown that Gaussian doped channel Junctionless Tunnel Field Effect Transistor purveys higher ION/IOFF ratio, lower threshold voltage and sub-threshold slope and also offers better short channel performance as compared to JLTFET with uniformly doped channel.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in I OFF of ～ 9 × 10 -16 A/ μ m, I ON of ～20 μ A/ μ m, I ON /I OFF of ～2 × 10 10 , threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO 2 /InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low- k spacer thickness of 10 nm and V DD of 0.2 V.

Nanoscale III-V on Si-based junctionless tunnel transistor for EHF band applications

A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor (SG-JLTFET) has been reported which shows excellent dc characteristics at low power supply operation. This device has a thin uniformly n-type doped channel of GaSb i.e. gallium antimonide which is grown epitaxially over silicon substrate. The DC performance parameters such as I ON , I ON / I OFF , average and point subthreshold slope as well as device parameters for analog applications viz. transconductance g m , transconductance generation efficiency g m / I D , various capacitances and the unity gain frequency f T are studied using a device simulator. Along with examining its endurance to short channel effects, the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET (DG-JLTFET). The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.

A novel uniformly doped barrier modulated ultra-deep-submicron poly-Si thin film transistor with very low subthreshold slope

In this paper, the characteristics of a novel device structure, uniformly doped ultra-deep-submicron poly-Si barrier modulated thin film transistor (BM-TFT), are investigated and compared with conventional poly-Si TFT. Use of uniform doping provides a solution from problems associated with random dopant fluctuations. The suppression of the leakage current of the TFT by introducing barrier modulation is verified and presented. The device is optimized with respect to channel length, doping of channel, spacer dielectric and gate dielectric material. Simulations resulted in I OFF of ~2 × 10−11 A μm−1, I ON of ~2mA μm−1, I ON/I OFF of 108, subthreshold slope of 144 mV/dec and DIBL of 119 mV V−1 for PolyGate/HfO2/Poly-Si coplanar BM-TFT at temperature. of 300 K, gate length of 60 nm, oxide thickness of 5 nm, film thickness of 10 nm, low-k spacer thickness of 20 nm and V DD of 2.5 V.