Baik-Woo Lee

A novel and simple fabrication technology for high power module with enhanced thermal performance

A novel packaging method for high power modules based on one-step sintering process using a proper jig and nano silver paste is described. First, using Ansoft Q3D Extractor, electromagnetic simulation is carried out to design the best chip array and DC bus connection, which giving the lowest stray inductance. A die-bonder is used for a precise die attachment, which provides high placement accuracy (<; 25 μm). One step sintering process between Si chip to DBC and DBC to baseplate was established under a low temperature (<; 260 °C) and low pressure (<; 10 MPa). In addition, the relation of the porosity and pressure on the adhesion of sintered silver layers was investigated. Finally, thermal performance of the proposed package and cooling is then evaluated with both FEA (finite element analysis) simulation and experiments. The simulation and experimental results, which show the lowest value (<;0.09 °C/W) of thermal resistance of junction to fluid, agree well.

Novel Chip-Last Method for Embedded Actives in Organic Packaging Substrates

Embedded actives are to bury thinned active chips into package substrates, as opposed to surface mounted devices (SMDs), which can achieve smaller form factor, better electrical performance and higher functionality than the SMD technology. While many embedded actives have been explored so far, they are based on chip-first and -middle approaches, in which the active chips are embedded before and during the build-up processes of package substrates, respectively. The most concern with those two current approaches is the loss accumulation associated with the build-up layer processes carried out right on top of the embedded chips, which is highly likely to lose the embedded chips during their packaging process. The reworkability to replace the faulty chips embedded with good ones and thermal management of the embedded chips are also issues since the embedded chips are totally surrounded by hard-cured polymers. In this paper, chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging. In the chip-last approach, a cavity is introduced within the build-up layers of package substrate and a chip is directly embedded into the cavity. A first proto-type of the chip-last embedded active will be demonstrated by developing various cavity formation processes within the build-up layers and then embedding 100 μm thick chips into the defined cavities.