Jae-joon Oh

Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

Highly reliable 50nm contact cell technology for 256Mb PRAM

Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.

Writing current reduction for high-density phase-change RAM

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

Effects of TMAH Treatment on Device Performance of Normally Off

Normally off Al2O3/GaN MOSFETs are fabricated by utilizing a simple tetramethylammonium hydroxide (TMAH) treatment as a postgate-recess process. The TMAH-treated device with a gate length of 2.5 μm exhibited excellent device performances, such as a threshold voltage of 3.5 V, a maximum drain current of 336 mA/mm, and a breakdown voltage of 725 V, along with extremely small gate leakage current of about 10-9 A/mm at Vgs = 15 V, which is approximately six orders lower in magnitude compared to that of the device without TMAH treatment.

\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GaN}

The impact of gate metals on the threshold voltage (VTH) and the gate current of p-GaN gate high-electron-mobility transistors (HEMTs) is investigated by fabricating p-GaN gate HEMTs with different work function gate metals-Ni and W. p-GaN gate HEMTs incorporate a p-GaN layer under the gate electrode as the gate stack on top of the AlGaN/GaN layer. In comparison to the Ni-gate p-GaN HEMTs, the W-gate p-GaN HEMTs showed a higher VTH of 3.0 V and a lower gate current of 0.02 mA/mm at a gate bias of 10 V. Based on TCAD device simulations, we revealed that these high VTH and low gate current are attributed to the low gate metal work function and the high Schottky barrier between the p-GaN and the W gate metal.

MOSFET

This letter studies the current collapse phenomenon during switching in p-GaN gate AlGaN/GaN high-electron-mobility transistors. It is found that channel hot electrons play a major role in increasing the current collapse and that adding a field plate significantly reduces the effect. By stressing the device with OFF-state pulses of 100 μs× 10 μs with a VGS rise/fall time of 10 ns at Vdc 400 V, compared to the ON-resistance before stress, the ON-resistance was 78 times larger after stress without field plates. With a field plate, it was only 1.8 times larger.

p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current

A novel MRAM structure using current induced switching is implemented and evaluated. The current for switching, assisted by local field, was 1mA with 19 % magneto-resistance at 100 mV bias voltage. 0.2/spl times/0.3 /spl mu/m/sup 2/ magnetic elements were integrated with standard CMOS process and a magnetic tunnel junction was optimized to obtain enough sensing signal. The resistance of tunnel junction was controlled to improve sensing margin. The novel structure has the possibility of reducing cell size to 6F, in which digit lines are unnecessary, and can minimize the writing disturbance. This novel structure is the excellent candidate for MRAM as one of universal memory.

Impact of Channel Hot Electrons on Current Collapse in AlGaN/GaN HEMTs

In this paper, magnetic and electrical properties of the MTJs have been investigated at each fabrication step of the full integration with carefully designed parameters of M-H and I-V properties and TMR properties of 64Kb MRAM with minimal process induced damages have been achieved.