Balkaran Gill

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

Combinational Logic Soft Error Correction

We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniques

On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies

Test chips built in a 32nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique referred to as RCC (Reinforcing Charge Collection). This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.

Soft Error Susceptibilities of 22 nm Tri-Gate Devices

We report on measured radiation-induced soft error rates (SER) of memory and logic devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate excellent single event upset (SEU) scaling benefits of tri-gate devices. For cosmic radiation, SEU SER reduction levels of the order of are observed relative to 32 nm planar devices, while for alpha-particles, the measured SEU SER benefit is in excess of . Similar improvements are observed for Tri-Gate combinational logic and memory array multi-cell upset (MCU) rates. Reduced SER (RSER) device SER performances (relative to standard, non -RSER devices) are on par or better than that of tested 32 nm planar devices. Finally, a novel, efficient SER reduction design called RTS is introduced.

Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.

Radiation-induced clock jitter and race

The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.

Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.

Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

We report on radiation-induced soft error rate (SER) improvements in the 14-nm second generation high- k + metal gate bulk tri-gate technology. Upset rates of memory cells, sequential elements, and combinational logic were investigated for terrestrial radiation environments, including thermal and high-energy neutrons, high-energy protons, and alpha-particles. SER improvements up to ~ 23× with respect to devices manufactured in a 32-nm planar technology are observed. The improvements are particularly pronounced in logic devices, where aggressive fin depopulation combined with scaling of relevant fin parameters results in a ~ 8× reduction of upset rates relative to the first-generation tri-gate technology.

The Susceptibility of 45 and 32 nm Bulk CMOS Latches to Low-Energy Protons

We measured low-energy proton radiation induced soft error rates (SER) of standard and reduced-SER (RSER) latches, manufactured in 32 nm and 45 nm bulk CMOS technologies, and conclude that sequential logic elements built in these technologies are not yet susceptible. Further, our results demonstrate that at proton energies where direct ionization dominates, critical charge (Qcrit) plays a far bigger role than at proton energies above the nuclear reaction threshold.

Correlating low energy neutron SER with broad beam neutron and 200 MeV proton SER for 22nm CMOS Tri-Gate devices

For terrestrial single event upset (SEU) characterization, JEDEC JESD89A requires using either broad beam neutron sources or at least four single neutron/proton particle energy sources. While computing ambient upset rates from broad beam neutron sources, such as the ICE House at Los Alamos Neutron Science Center (LANSCE), is simple and direct, their availability, cost, and particle fluxes are very limited. Several authors in the open literature therefore have considered alternatives, such as high energy (e.g., 200 MeV) proton beams or low energy (e.g., 14MeV) neutron beams. In this paper, we address the questions of accuracy and correlation when these alternative facilities are employed. SEU data were collected on 22nm Tri-Gate bulk CMOS devices at Boeing (BREL), Los Alamos (LANSCE/WNR) and IUCF (RERP and LENS) and the corresponding upset rates are compared.