Norbert Seifert

Robust system design with built-in soft-error resilience

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A systems susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

Combinational Logic Soft Error Correction

We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniques

Timing vulnerability factors of sequentials

Single-event upsets (SEU) from particle strikes have become a key challenge in microprocessor design. Modern superpipelined microprocessors typically contain many thousands of sequentials whose soft-error rate (SER) cannot be neglected any more. An accurate assessment of the SER of sequentials is therefore crucial. This work describes a method for computing timing vulnerability factors (TVFs) of sequentials. Our methology captures the impact of the circuit environment which sequentials are typically placed in. Further, upsets occurring in local clock nodes have been accounted for. Results are presented for master-slave type flip flops and for flow-through latches of a high-performance microprocessor. Our investigations demonstrate that TVFs are a strong function of the propagation delay of the combinational logic and typically vary between /spl sim/0% and 50%. For high-performance microprocessors, we predict average TVF values of the order of 20%-30%. Further, we expect TVFs to be largely technology independent for the same design.

Chip-level soft error estimation method

This paper gives a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs. It summarizes the physics and silicon process dependencies of soft error mechanisms and describes the determination of SERs for basic circuit types. It reviews the impact of logical and architectural filtering on SER calculations and focuses on the structural filtering of soft radiation events by nodal timing mechanisms.

On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies

Test chips built in a 32nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique referred to as RCC (Reinforcing Charge Collection). This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.

Soft Error Susceptibilities of 22 nm Tri-Gate Devices

We report on measured radiation-induced soft error rates (SER) of memory and logic devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate excellent single event upset (SEU) scaling benefits of tri-gate devices. For cosmic radiation, SEU SER reduction levels of the order of are observed relative to 32 nm planar devices, while for alpha-particles, the measured SEU SER benefit is in excess of . Similar improvements are observed for Tri-Gate combinational logic and memory array multi-cell upset (MCU) rates. Reduced SER (RSER) device SER performances (relative to standard, non -RSER devices) are on par or better than that of tested 32 nm planar devices. Finally, a novel, efficient SER reduction design called RTS is introduced.

Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.

Logic soft errors in sub-65nm technologies design and CAD challenges

Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.