Victor Zia

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.

Logic soft errors: a major barrier to robust platform design

Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques