Banafsheh Barabadi

Electrowetting-on-dielectric actuation of a vertical translation and angular manipulation stage

Adhesion and friction during physical contact of solid components in microelectromechanical systems (MEMS) often lead to device failure. Translational stages that are fabricated with traditional silicon MEMS typically face these tribological concerns. This work addresses these concerns by developing a MEMS vertical translation, or focusing, stage that uses electrowetting-on-dielectric (EWOD) as the actuating mechanism. EWOD has the potential to eliminate solid-solid contact by actuating through deformation of liquid droplets placed between the stage and base to achieve stage displacement. Our EWOD stage is capable of linear spatial manipulation with resolution of 10 μm over a maximum range of 130 μm and angular deflection of approximately ±1°, comparable to piezoelectric actuators. We also developed a model that suggests a higher intrinsic contact angle on the EWOD surface can further improve the translational range, which was validated experimentally by comparing different surface coatings. The capabilit...

Rapid multi-scale transient thermal modeling of packaged microprocessors using hybrid approach

This paper studies the rapid transient thermal analysis of a packaged high power microprocessor, forced convection cooled using a heat sink. A spatially resolved power map for Intel Core 2 Duo Penryn processor was considered. Two different transient power profiles were investigated: an impulsively applied power map, and an oscillatory variation power map. We extended and demonstrated the capability of a recently developed hybrid approach in modeling several decades of length scale from package to chip at a considerably lower computational cost, while maintaining satisfactory accuracy. The proper orthogonal decomposition (POD) technique was used for the rapid prediction of the transient thermal response for impulsive vs. oscillatory power applied to the chip. The results were compared with a detailed finite element (FE) model developed in COMSOL®. The close agreement between the two models confirms the capability of the multi-scale model in rapidly predicting accurate temperature profiles, without performing detailed FE simulations, which can significantly decrease the computational cost in parametric modeling.

Parametric study of thin film evaporation from nanoporous membranes

The performance and lifetime of advanced electronics are often dictated by the ability to dissipate heat generated within the device. Thin film evaporation from nanoporous membranes is a promising thermal management approach, which reduces the thermal transport distance across the liquid film while also providing passive capillary pumping of liquid to the evaporating interface. In this work, we investigated the dependence of thin film evaporation from nanoporous membranes on a variety of geometric parameters. Anodic aluminum oxide membranes were used as experimental templates, where pore radii of 28–75 nm, porosities of 0.1–0.35, and meniscus locations down to 1 μm within the pore were tested. We demonstrated different heat transfer regimes and observed more than an order of magnitude increase in dissipated heat flux by operating in the pore-level evaporation regime. The pore diameter had little effect on pore-level evaporation performance due to the negligible conduction resistance from the pore wall to ...

Prediction of Transient Thermal Behavior of Planar Interconnect Architecture Using Proper Orthogonal Decomposition Method

A major challenge in maintaining quality and reliability in today’s microelectronics devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Cyclic thermal events during operation, stemming from Joule heating of the metal lines, can lead to fatigue failure due to the varying thermal expansion coefficients of the different materials that compose the microchip package. To aid in the avoidance of such device failures, it is imperative to develop a predictive capability for the thermal response of micro-electronic circuits. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous system using a reduced order modeling approach of the Proper Orthogonal Decomposition (POD) method and Galerkin Projection Technique. This study considers an interconnect structure embedded in the bulk of a microelectronic device. The effect of different types of current pulses, pulse duration, and pulse amplitude were investigated. By using a representative step function as the heat source, the model predicted the exact transient thermal behavior of the system for all other cases without generating any new observations, using just a few POD modes. To validate this unique capability, the result of the POD model was compared with a finite element (FE) model developed in LS-DYNA®. The behaviors of the POD models were in good agreements with the corresponding FE models. This close correlation provides the capability of predicting other cases based on a smaller sample set which can significantly decrease the computational cost.Copyright

Multiscale Transient Thermal Analysis of Microelectronics

In a microelectronic device, thermal transport needs to be simulated on scales ranging from tens of nanometers to hundreds of millimeters. High accuracy multiscale models are required to develop engineering tools for predicting temperature distributions with sufficient accuracy in such devices. A computationally efficient and accurate multiscale reduced order transient thermal modeling methodology was developed using a combination of two different approaches: “progressive zoom-in” method and “proper orthogonal decomposition (POD)” technique. The capability of this approach in handling several decades of length scales from “package” to “chip components” at a considerably lower computational cost, while maintaining satisfactory accuracy was demonstrated. A flip chip ball grid array (FCBGA) package was considered for demonstration. The transient temperature and heat fluxes calculated on the top and bottom walls of the embedded chip at the package level simulations are employed as dynamic boundary conditions for the chip level simulation. The chip is divided into ten function blocks. Randomly generated dynamic power sources are applied in each of these blocks. The temperature rise in the different layers of the chip calculated from the multiscale model is compared with a finite element (FE) model. The close agreement between two models confirms that the multiscale approach can predict temperature rise accurately for scenarios corresponding to different power sources in functional blocks, without performing detailed FE simulations, which significantly reduces computational effort. [DOI: 10.1115/1.4029835]

Thermal characterization of planar interconnect architectures under different rapid transient currents using the transmission line matrix and finite element methods

Considering the increasing level of integration and high current densities, the quality and reliability of interconnects in microelectronics is a major challenge. This work studied the problem of transient Joule heating in 180 nm by 360 nm interconnects in a two-dimensional (2D) inhomogeneous model. Specifically, the effects of the duration and amplitude of rapid square-wave source current pulses (100 ns and 1 µs) were investigated. The transmission line matrix (TLM) method was implemented with the link-resistor (LR) formulation and the results were compared with a finite element (FE) model that was developed in LS-DYNA®. This comparison showed that the overall behavior of the TLM models were in good agreement with the corresponding FE models while, near the heat source, the transient TLM solutions developed slower than the FE solutions. Overall, computational efficiency of the TLM method and its ability to accept non-uniform 2D and 3D mesh and variable time-step make it a good candidate for multi-scale analysis of Joule heating in interconnects.

Thermal Characterization of Planar Interconnect Architectures Under Transient Currents

The quality and reliability of interconnects in microelectronics is a major challenge considering the increasing level of integration and high current densities. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous model. The transmission line matrix (TLM) method was implemented with link-resistor (LR) and link-line (LL) formulations, and the results were compared with a finite element (FE) model that was developed in LSDyna. This comparison showed that the overall behavior of the TLM models were in good agreement with the FE model while, near the heat source, the transient TLM solutions developed slower than the FE solution. The steady-state results of the two models were identical. The two TLM formulations yielded slightly different transient results, with the LL result growing slower particularly at the source boundary and becoming unstable at short time-steps. It was concluded that the LR formulation is more accurate for transient thermal analysis. Computational efficiency of the TLM method and its ability to accept non-uniform 2D and 3D mesh and variable time-step makes it a good candidate for multi-scale analysis of Joule heating in the interconnects.© 2009 ASME

High heat flux evaporation from nanoporous silicon membranes

We investigated the evaporative cooling performance of a nanoporous membrane based thermal management solution designed for ultra-high heat flux dissipation from high performance integrated circuits. The biporous evaporation device utilizes thermally-connected, mechanically-supported, high capillarity membranes that maximize thin film evaporation and high permeability liquid supply channels that minimize viscous pressure losses. The 600 nm thick membrane was created on a silicon on insulator (SOI) wafer, fusion-bonded to a separate wafer with larger liquid channels. Overall device performance arising from non-uniform heating and evaporation of methanol was captured experimentally. Heat fluxes up to 412 W/cm2 over an area of 0.4×5 mm, at a temperature rise of 24.1 K from the heated substrate to ambient vapor, were obtained. These results are in good agreement with a high-fidelity coupled fluid convection and solid conduction compact model that incorporates non-equilibrium and sub-continuum effects at the liquid-vapor interface. This work provides a proof-of-concept demonstration of our biporous evaporation device. Simulations of the validated model at optimized operating conditions and with improved working fluids, predict heat dissipation in excess of 1 kW/cm2 with a device temperature rise under 30 K, for this scalable cooling approach.

Multi-Scale Transient Thermal Analysis of Microelectronics

Thermal transport in microelectronic devices spans length scales from tens of nanometers to hundreds of millimeters. One of the major challenges in maintaining quality and reliability in today’s microelectronic devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Consequently, significant opportunities for energy efficiency exist at various levels of the length scale hierarchy by optimization of thermal management resources.In this study, we developed a computationally efficient and accurate multi-scale reduced order transient thermal methodology consisting of hybrid implementation of two different multi-scale approaches: 1. “Progressive Zoom-in” method and 2. “Proper Orthogonal Decomposition (POD)” technique. The suggested approach provides the ability to predict different thermal scenarios based on one representative thermal scenario, while maintaining the desired spatial and temporal accuracy. In this paper, a Flip Chip Ball Grid Array (FCBGA) package was considered for hybrid modeling. To demonstrate the capability of POD method in predicting different thermal scenarios, the chip is divided into ten function blocks. Each of these blocks had a different randomly generated dynamic power source. To validate this methodology, the results were compared with a finite element (FE) model developed in COMSOL®. The behavior of the POD model was in good agreements with the corresponding FE model. This close correlation provides the capability of predicting other thermal scenarios based on a smaller sample set which can significantly decrease the computational cost.© 2012 ASME

Interconnect Joule Heating under Transient Currents using the Transmission Line Matrix Method

The quality and reliability of interconnects in microelectronics is a major challenge considering the increasing level of integration and high current densities. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous domain using the transmission line matrix (TLM) method. Computational efficiency of the TLM method and its ability to accept non-uniform 2D and 3D mesh and variable time step makes it a good candidate for multi-scale analysis of Joule heating in on-chip interconnects. The TLM method was implemented with link-resistor (LR) and link-line (LL) formulations, and the results were compared with a finite element (FE) model. The overall behavior of the TLM models were in good agreement with the FE model while, near the heat source, the transient TLM solutions developed slower than the FE solution. The steady-state results of the TLM and FE models were identical. The two TLM formulations yielded slightly different transient results, with the LL result growing slower, particularly at the source boundary and becoming unstable at short time-steps. It was concluded that the LR formulation is more accurate for transient thermal analysis.