Bang W. Lee

Design of a neural-based A/D converter using modified Hopfield network

The architecture associated with the Hopfield network can be utilized in the VLSI realization of several important engineering optimization functions for signal processing purposes. The properties of local minima in the energy function of Hopfield networks are investigated. A design technique to eliminate these local minima in the Hopfield neural-based analog-to-digital converter has been developed. Experimental data agree well with theoretical results in the output characteristics of the neural-based data converter. >

Modified Hopfield neural networks for retrieving the optimal solution

Due to the rugged energy function of the original Hopfield networks, the output is usually one local minimum in the energy function. An analysis on the locations of local minima in Hopfield networks is presented, and a modified network architecture to eliminate such local minima is described. In particular, another amplifier is introduced at the processor nodes to give correction terms. This modified Hopfield network has been successfully applied to the construction of analog-to-digital converters with optimal solutions. Experimental results on the voltage transfer characteristics of data converters are presented.

An integrated-circuit reliability simulator-RELY

A prototype very-large-scale integrated circuit (VLSI) reliability simulator is described. Software modules for hot-carrier effects have been developed. Popular substrate current models are implemented in the simulator. Experiments were performed to establish the relationship between transistor model parameter changes and the substrate current level. The circuit reliability simulation techniques can be extended to include dielectric breakdown and interconnect electromigration effects. >

Paralleled hardware annealing for optimal solutions on electronic neural networks

Three basic neural network schemes have been extensively studied by researchers: the iterative networks, the backpropagation networks, and the self-organizing networks. Simulated annealing is a probabilistic hill-climbing technique that accepts, with a nonzero but gradually decreasing probability, deterioration in the cost function of the optimization problems. Hardware annealing, which combines the simulated annealing technique with continuous-time electronic neural networks by changing the voltage gain of neurons, is discussed. The initial and final voltage gains for applying hardware annealing to Hopfield data-conversion networks are presented. In hardware annealing, the voltage gain of output neurons is increased from an initial low value to a final high value in a continuous fashion which helps to achieve the optimal solution for an optimization problem in one annealing cycle. Experimental results on the transfer function and transient response of electronic neural networks achieving the global minimum are also presented.

A high slew-rate CMOS amplifier for analog signal processing

The performances of several types of analog VLSI circuits are limited by the setting behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS service using a 2- mu m scalable CMOS technology. When biased at a DC power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/ mu s, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB and 50 kHz. >

Hardware annealing in electronic neural networks

A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzmann machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented. >

General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons

Circuit cells for DRAM-style programmable synapses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution. >

A compact and general-purpose neural chip with electrically programmable synapses

A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm/sup 2/ area using the 2- mu m scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1- mu m CMOS technologies.<<ETX>>

Self-reconstructing technique for expert system-based analog IC designs

The flexible-architecture approach to expert-system-based analog IC designs is presented. The self-reconstructing technique which uses circuit primitives as replacement parts in a design is described. The expert system used is capable of making an intelligent initial choice among circuits of fixed architecture as well as reconstructing the selected circuit to better satisfy a given set of performance specifications. Software implementation and experimental results are shown to demonstrate the power of the approach. >

Data flow processor for multi-standard video codec

In multimedia digital video applications, international standards such as JPEG, MPEG, and H.261 are widely adopted. Many DSP architectures have been proposed to meet requirements on the digital video. In this paper, a static data flow architecture containing nine parallel processors is described. Each processor made with a specialized hardware engine such as DCT and quantizer operates asynchronously and independently on its own data presence. This proposed DSP is fabricated in a 0.8 /spl mu/m triple metal technology with 16/spl times/16 mm/sup 2/ die area over 1.5 million transistors. The peak computing capability over 1 billion operations per second can provide full programmability for any DCT based digital video compression standards.<<ETX>>