Joongho Choi

A VLSI neural processor for image data compression using self-organization networks

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.

A high-precision VLSI winner-take-all circuit for self-organizing neural networks

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2- mu m CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks. >

A programmable analog VLSI neural network processor for communication receivers

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 mu m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure. >

An analog neural network processor for self-organizing mapping

The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2- mu m CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.<<ETX>>

A monolithic GaAs receiver for optical interconnect systems

A monolithic GaAs optical receiver which includes a photodetector and preamplifier was designed and fabricated using a common 1.0-/spl mu/m GaAs MESFET technology. The optical receiver operates at the data rate of 1 Gb/s. The transimpedance value can be continuously tuned from 1 to 10 k/spl Omega/. The metal-semiconductor-metal photodiode shows a 35% efficiency. Several design factors are considered to achieve high-bandwidth and low-noise operation. An array of the integrated receivers can be compactly implemented in a single chip for high-speed interconnection networks and photonic signal processing. >

Programmable-weight building blocks for analog VLSI neural network processors

Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it because of the serial hardware configuration. By using the analog circuit design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy requirements for neural operation can be satisfied. Components for a general-purpose neural chip have been designed and fabricated. Dynamically adjusted weight value storage provides programmable capability. Possible reconfigurable schemes for a general-purpose neural chip are also presented. Test of the prototype neural chip has been successfully conducted and an expected result has been achieved.

Photonic Neural Networks

The prospects of optical computing are well reported by T. Kaminuma, et al. [1]. Their view is described below. Coherence, i.e. in-phase, laser light can be guided to pass through two convex lenses as a broad parallel beam. If an object of varying light intensity was placed in front of the first lens, the output of the second lens will be a copy of the original image with a reversed orientation. In such an arrangement, the image has gone through a 2-dimensional Fourier transformation by the first lens and brought to its focal point. The transformed result actually undergoes a reverse Fourier transform by the second lens so that the final result is reversed left-to-right and top-to-bottom.

A compact low-power VLSI transceiver for wireless communication

A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 /spl mu/m CMOS technology from the MOSIS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for battery-powered devices, such as portable terminals. Design technologies can be applied to future high-speed wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased.

A Gaussian synapse circuit for analog VLSI neural networks

Back-propagation neural networks with Gaussian function synapses have a better convergence property over those with linear-multiplying synapses. A compact analog Gaussian synapse cell which is not biased in the subthreshold region has been designed for fully-parallel operation. This cell can approximate a Gaussian function with accuracy around 98% in the ideal case. Device mismatch induced by fabrication process will cause some degradation to this approximation. Programmability of the proposed Gaussian synapse cell is achieved by changing the stored synapse weight W/sub ji/, the reference current and the sizes of transistors in the differential pair.<<ETX>>