Bongjin Kim

Low-Complexity Tree Architecture for Finding the First Two Minima

This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of comparators by reusing the intermediate comparison results computed for the first minimum in order to collect the candidates of the second minimum. As a result, the proposed tree architecture improves the area-time complexity remarkably.

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns

In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. For a (40, 33) code, the proposed architecture reduces the latency and the hardware complexity by ~32% and 9%, respectively, compared with the most recent implementation.

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

This paper proposes a novel decoding algorithm to enhance the throughput of turbo decoding in LTE-Advanced systems and its hardware realization. The proposed method completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not degrade error-correcting performance for high-rate codes which are essential to achieve the maximum data rate of LTE-Advanced systems. The proposed method called tail-overlapped decoding can be easily applied to the conventional parallel decoding architecture designed for standardized communication systems. In addition, a new structure for the extrinsic information memory is proposed to eliminate memory contentions. A 3GPP LTE-Advanced turbo decoder supporting both decoding methods is implemented in 0.13 μm CMOS technology to show the effectiveness of the proposed algorithm. The decoder exhibits a decoding rate greater than 1Gbps with six iterations, meeting the peak data rate of the LTE-Advanced standard with much less hardware complexity than those of the previous works.

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes

To provide near-optimal error-correcting performance for multi-rate turbo codes and minimize the size of additional memory, a new decoding method is proposed in this paper. The proposed decoding is based on two methods: hybrid sliding window and dynamic metric encoding. The new window scheme combines dummy metric calculation and border metric storing methods to halve the border metric memory and improve the error-correcting performance for multi-rate codes. The dynamic encoding of metrics also significantly reduces the border metric memory without degrading the performance. Employing the two proposed methods reduces the conventional border metric memory by 83%. In addition, the superb error-correcting performance of the proposed method is verified for various code rates by conducting intensive simulations for 3GPP LTE codes.

QC-LDPC Decoding Architecture based on Stride Scheduling

In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. Furthermore, the decoder adopts a novel scheduling scheme, named as stride scheduling, to remove the conventional flexible permutation network and also minimize the number of memory accesses. The synthesized decoder costs 49K of logic gates and 54,144 bits of memory, while maintaining the throughput over the requirement of the WiMAX.

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders

In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding

To increase the throughput of turbo decoding, a new decoding method is proposed in this letter. The proposed method performs two decoding phases, in-ordered and interleaved ones, simultaneously by using two SISO decoders, which is completely contrast to the conventional decoding approach that conducts one of the two phases alternatively. The two SISO decoders exchange their outputs immediately to accelerate the update of extrinsic information and in turn to reduce the overall decoding latency, increasing the throughput by almost two times. Moreover, the proposed decoding method can be applied to any turbo code specified in communication standards, because it is not necessary to modify the encoding process. The effectiveness of the proposed method is verified from intensive simulations conducted for 3GPP LTE-Advanced codes.

Dual-rail decoding of low-density parity-check codes

In this paper, a new scheduling scheme is proposed to increase the throughput of a low-density parity-check decoder by maximizing resource utilization. The operations of check nodes and variable nodes are fully overlapped in the proposed scheduling to achieve maximized utilization of hardware resources, which in turn increases the throughput and reduces the overall decoding latency. Moreover, no restriction is posed on the formation of the parity check matrix. To verify the effectiveness of the proposed scheme, a series of simulations is performed for irregular random LDPC codes with considering additive white Gaussian noise channel.