Baosheng Wang

Methodologies and algorithms for testing switch-based NoC interconnects

In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.

Fast detection of data retention faults and other SRAM cell open defects

Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode

The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) technique that we refer to as No Write Recovery Test Mode (NWRTM) to detect all open defects, some of which produce Data Retention Faults (DRFs) but are undetectable by typical March tests. We demonstrate the effectiveness of our proposed technique by only applying it to fault-free memory cells and faulty cells with those undetectable defects but all the open defects are covered since our DFT technique is implemented by simply adding extra test cycles into typical March tests. Two 6T SRAM cell models, one a high-speed version and the other a low-power one, representing extreme cases according to traditional design methodologies, were designed to validate our proposed NWRTM at the circuit level. Simulation results show that our NWRTM amounts to a shorter total test time and improved open defect detection capability. In addition, in comparison to other DFT techniques, NWRTM requires the least additional design effort, and imply less area and no performance penalties.

Reducing test time of embedded SRAMs

Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology, while maintaining the same defect and fault coverage.

Test/Repair Area Overhead Reduction for Small Embedded SRAMs

For current highly-integrated and memory-dominant system-on-a-chips (SoCs), especially for graphics and networking SoCs, the test/repair area overhead of embedded SRAMs (e-SRAMs) is a big concern. This paper presents various approaches to tackle this problem from a practical point of view. Without sacrificing at-speed testability, diagnosis capability and repairability, the proposed approaches consider partly sharing wrapper for identical memories, sharing memory BIST controllers for e-SRAMs embedded in different functional blocks, test responses compression for wide memories, and various repair strategies for e-SRAMs with different configurations. By combining the above approaches, the test/repair area overhead for e-SRAMs can be significantly reduced. For example, for one benchmark SoC used in our experiments, it can be reduced as much as 10% of the entire memory array

Reducing embedded SRAM test time under redundancy constraints

Increasingly dense SRAMs of various bit capacities, embedded within current and future systems-on-a-chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and non-DRFs is growing rapidly. In this paper, we consider the overall production gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22 nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are.

Yield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing

This paper extends the model in (Wajih Dalai et al, Proc. of Int. Test Conf., p.518-523, 1999) to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixture impact. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (defects per million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.