Bapiraju Vinnakota

Monitoring power dissipation for fault detection

In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying specific test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not affect static power dissipation. We also discuss how faults may be detected with a frequency domain analysis. In many cases, the Fourier spectra of the power supply currents in the good and faulty circuits will be very different. Power monitoring is also verified experimentally, for an example circuit.

Defect-oriented test scheduling

As tester complexity and cost increase, reducing test time is an important manufacturing priority. Test time can be reduced by ordering tests so as to fail defective units early in the test process. Algorithms to order tests that guarantee optimality require execution time that is exponential in the number of tests applied. We develop a simple polynomial-time heuristic to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. An ordering algorithm requires information on the ability of tests to detect defective units. One way to obtain this information is by simulation. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this subset is representative. The ordering heuristic was applied to manufactured digital and analog integrated circuits (ICs) tested with commercial testers. When both approaches work, the orders generated by the heuristic are optimal. More importantly, the heuristic is able to generate an improved order for large problem sizes when the optimal algorithm is not able to do so. The new test orders result in a significant reduction, as high as a factor of four, in the time needed to identify defective units. We also assess the validity of using such sampling techniques to order tests.

Process-tolerant test with energy consumption ratio

We develop a new technique for fault detection based on a new metric, the energy consumption ratio (ECR). ECR-based test can detect faults, such as redundant faults, that escape detection with other techniques. Though the ECR is a metric based on the supply current, an analog parameter, it is remarkably tolerant to the impact of process variations. The quality of ECR-based test is demonstrated through extensive simulation on a process offered by MOSIS. We also present a test generation algorithm for the new test technique. When applied to benchmark circuits, this technique reliably detects a large fraction of the combinationally redundant faults in them.

Statistical threshold formulation for dynamic I/sub dd/ test

Dynamic I/sub dd/ techniques can potentially address the limitations of traditional test techniques and the Idd, test. Normal process variations in manufacturing affect dynamic Idd techniques in two ways. Since a fault-free circuit can produce a range of responses, they necessitate the use of a threshold-based test process. Process variations also degrade the resolution and consequently the fault coverage of a test technique. The authors develop statistical techniques to set thresholds in a dynamic Idd test process. The techniques use Principal Component Analysis, a statistical analysis technique,. to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic tests and to tests based on the energy consumption ratio (ECR). The ECR is a new test metric which offers several advantages, including tolerance to process variations, over other dynamic test techniques. The authors demonstrate that their techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of their knowledge, this is the first systematic technique to set thresholds for a dynamic I/sub dd/ test method.

Synthesis of sequential circuits for parallel scan

Sequential circuit testing is known to be a difficult problem. The authors present a synthesis for testability (SFT) method to solve this problem. In this approach, some testability features analogous to the traditional scan design are added to the normal logic equations which define the finite state machine (FSM). The augmented FSM is then synthesized with these added features built in. The overhead may thus be reduced as the logic needed to obtain testability is merged with the logic needed for normal functionality. Another advantage of this approach is that the test set length is usually very small; in many cases, the authors obtain a sequential test which is roughly only twice the size of the combinational test set derived for the combinational logic of the sequential circuit. This drastically reduces the test application time without sacrificing the advantages of scan design: high fault coverage and low test generation time. By applying their method to benchmark FSM examples the authors show that the resultant area overhead is also quite low.<<ETX>>

A dependence graph-based approach to the design of algorithm-based fault tolerant systems

A two-stage approach to the design of algorithm-based fault-tolerant (ABFT) systems is proposed. In the first stage a code is chosen to encode the data used in the algorithm. In the second stage the optimal architecture for implementing the scheme is chosen through the use of dependence graphs. Dependence graphs are a graph-theoretic form of algorithm representation. It is demonstrated that not all architectures are ideal for the implementation of a particular ABFT scheme. The authors propose new measures for characterizing the fault-tolerance capability of a system in order to better exploit the proposed design method. Dependence graphs can also be used for the synthesis of ABFT schemes for nonlinear problems. An example of a fault-tolerant median filter is provided to illustrate the usefulness of the dependence graph as a design tool for nonlinear system synthesis.<<ETX>>

Data parallel fault simulation

Fault simulation is a computer-intensive problem. Parallel processing is one method to reduce simulation time. In this paper, we discuss a technique to partition the fault set for fault-parallel simulation on multiple processors. When applied statically, the technique can scale well for up to 32 processors. The fault-set partitioning technique is simple and can itself be parallelized. Existing uniprocessor algorithms, based on parallel-pattern simulation, can be used for multiprocessor simulation without modification. Therefore, the techniques can be used effectively on a low-cost parallel resource such as a network of workstations.

The design of analog self-checking circuits

In this paper we introduce a new class of analog circuits, self-checking analog circuits. We develop and discuss methods to design members of this new class. We target the class of fully differential analog circuits and use the inherent dual-rail code to develop self-checking circuits. We describe the design of a self-checking operational amplifier and the associated subcircuits. Our methodology has wide application as many analog circuits already are or can be transformed into fully differential circuits.<<ETX>>

Combining dictionary coding and LFSR reseeding for test data compression

In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

DFT for digital detection of analog parametric faults in SC filters

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.