Larry L. Kinney

C-Testability of Two-Dimensional Iterative Arrays

The issue of testing two-dimensional iterative arrays with a constant number of test vectors independent of the array size (C-testability) is discussed in this paper. Sufficient conditions for C-testability are stated. It is shown that any two-dimensional array can be modified to become C-testable. An extension to systolic (synchronous) arrays is made. The approach simplifies testing systolic arrays by using one test vector to test many cells of the array in a periodic fashion. A two-dimensional array for matrix multiplication is used to illustrate the approach for systolic arrays.

A systematic approach to the design of digital bussing structures

Busses are vital elements of a digital system---they interconnect registers, functional modules, subsystems, and systems. As technological advances raise system complexity and connectivity, busses are being recognized as primary architectural resources which can frequently be the limiting factor in performance, modularity, and reliability. The traditional view of bussing as just an ad hoc way of hooking things together can no longer be relied upon to produce even viable much less cost-effective solutions to these increasingly sophisticated interconnect problems.

Combining dictionary coding and LFSR reseeding for test data compression

In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

Concurrent Error Detection in Sequential Circuits Using Convolutional Codes

Concurrent error detection schemes in digital systems are often based upon error-detecting codes. In [9], we presented a methodology for encoding the states of sequential machines using convolutional codes for on-line detection of sequencing errors. In conjunction with this methodology, we defined an equivalence relation on convolutional codes that exhaustively characterizes the possible transient error detection capabilities and complexities of sequential machine realizations based upon convolutional codes. In this paper, we determine the number of equivalence classes of (n, k, 1) convolutional codes generated by minimal encoders requiring k memory elements and provide a procedure for generating representatives from each equivalence class.

Error detection with latency in sequential circuits

An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with less complexity and greater error coverage than schemes based on block codes. The potential benefits this approach are demonstrated, including increased error coverage with simultaneous reductions in circuit complexity.<<ETX>>

Relating the cyclic behavior of linear and intrainverted feedback shift registers

Feedback shift registers (FSRs) are sometimes implemented with inversions between stages to improve their testability and their ability to locate faults. These intrainverted FSRs (IFSRs) can be realized with less overhead than standard linear feedback shift registers (LFSRs). It is shown how to relate the cyclic behavior of the LFSR and the corresponding IFSR, based on the same feedback polynomial, so that IFSRs can be designed to exploit the inherent implementation advantages while exhibiting the well-known behavior of LFSRs. In particular, it is shown that the cyclic and serial output behavior of LFSRs can be emulated by IFSRs when loaded with the appropriate initial states for most feedback shift register lengths and feedback polynomials. How the initial state for the IFSR can be derived, given the feedback polynomial and the initial state of the desired cycle in the LFSR, is described. Conditions under which such mapping of behavior cannot be guaranteed are given. >

Extension of the critical path tracing algorithm

Critical path tracing (CPT) is an approximate algorithm used for fast fault simulation, as part of test generation algorithms. It partitions the circuit to be simulated into fanout free regions in order to simplify decisions regarding the propagation of logic signal changes through the circuit. Presented are concepts that result in faster decision making than in CPT for many combinations of input changes. After true value simulation, improved critical path tracing (ICPT) does a more extensive classification of lines than CPT does. This finer classification determines propagation of fault effects without fault simulation in many cases where CPT may require fault simulation. The increase in execution time to incorporate the improvements is insignificant compared to the savings in simulation time for many input vectors. >

Serial Adders with Overflow Correction

A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

Decomposition of Asynchronous Sequential Switching Circuits

The problem of decomposing an asynchronous sequential circuit into the serial connection of two asynchronous sequential circuits is considered. Six types of serial connections are defined, and necessary and sufficient conditions are derived for making five of the six types of serial decomposition, while sufficient conditions are derived for the sixth. Systematic and constructive procedures are presented for making each of the decompositions.

Incremental test pattern generation

Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.<<ETX>>