Sadik C. Esener

Performance comparison between optoelectronic and VLSI multistage interconnection networks

The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. The bases of the comparison include speed, bandwidth, power consumption, and footprint area. The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2*2 bit-serial switching elements. CMOS technology was used in the VLSI implementation, and it is assumed that the entire network resides on a single chip. Regular free-space optical interconnects are used in the optoelectronic implementation. The results show that for large networks optoelectronics offers higher speed and lower area than VLSI. Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256. >

Free Space Optical Interconnects For Microelectronics And Parallel Computing

Free space optical interconnections offer some beneficial solutions to microelectronic problems, e.g., pin-ins, pin-outs, testing, and wafer scale integrations. When applied to an array of multiprocessors for parallel computing, free space interconnects can offer 3-D interconnection topology, 2-D parallel data inputs and outputs and shared memory architectures. Furthermore, if the optical interconnections are programmable, we shall be able to incorporate several computational architectures efficient for implementing several computational algorithms in one machine. In this review, many of these potential benefits of utilizing free space optical interconnections will be described in detail and various research topics currently under investigation at UCSD will be discussed.

Applications And Design Considerations For Optical Interconnects In VLSI

This paper introduces new applications and design tradeoffs anticipated for free space optical interconnections of VLSI chips. New implementations of VLSI functions are described that use the capability of making optical inputs at any point on a chip, and take advantage of greater flexibility in on-chip signal routing. These include N-port addressable memories, CPU clock phase distribution, hardware multipliers, dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper will focus on identifying the design issues, their possible solution, and their impact on VLSI design techniques.

Critical issues in free space intrachip optical interconnect technology

Conditions are determined for which free space optical interconnects can transmit information at a higher data rate and consume less power than the equivalent electrical interconnections. Effects of circuit dimension scaling and improved optical link efficiency are discussed. The packing densities of optical and electrical interconnects are also compared.

Holographic optical elements for slm defect removal and for optical interconnects

Holographic Optical Elements (HOEs) of space-variant impulse response have been designed and generated using a computerized optical system. HOEs made of dichromated gelatin have been produced and used for spatial light modulator defect removal and for optical interconnects. Experimental performance and characteristics are presented.

3-D Optical Memories For High Performance Computing.

The design of high performance computers such as array processors has reached a critical stage. These machines are increasingly using parallel processing methods to achieve higher performance. They require low cost memory systems with much higher capacities and bandwidths than available today while retaining small volume, weight, and power consumption characteristics. Massively interconnected optical computers will require even higher performance memory systems. This paper reviews various 3-D memory concepts that are proposed to meet these demands.

Phase locked vertical cavity surface emitting laser

A VCSEL amplifier has been phase locked to a master oscillator laser. The central frequency of the light may be slightly shifted, but by an amount which is significantly less than the linewidth of the signal. The coherence of the amplified light is not significantly degraded by frequency broadening or noise. These results suggest that a MOPA phased array using VCSEL amplifiers is feasible. Experiments to demonstrate a coherent 1x2 array with discrete VCSELs are at present ongoing.

A system architecture for use with free space optical interconnects in a 3D stacked processor environment

There exists a technology suited for dealing with the unique constraints of the 3D stacked processor environment; free space optical interconnects (FSOI). This technology uses VCSELs, vertical cavity surface emitting lasers, as a communications medium. FSOI has been proven to work in a two dimensional matrix format that would be optimal for communications between stacks.

Free-space Optical Interconnects For A One Kilobit RAM Chip

Free-Space Optical Interconnects for a One Kilobit RAM Chip M.R. Feldman, C.C. Guest, S.C. Esener, S.H. Lee and S . Krishnakumar, University of California, San Diego, La Jolla, CA. A.R. Johnston and R. Hartmayer, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA. Ademonstration system for free-space optical interconnects using a one kilobit RAM chip with integrated optical detectors, a semiconductor laser source, and a computer generated holographic optical element has been assembled and tested. Optical inputs onto the chip were used as row address signals to read data from the chip.

Justifications For A Hybrid Approach To Optical Computing

A hybrid approach to optical computing is currently studied at the University of California, San Diego for performing parallel processing. Figure 1 shows a promising parallel processing architecture, in which an optical processing array is connected massively in parallel to an optical memory array. An optical processing array consists of an array of electronic logic gates; each cell in the array has at least one photodetector (or phototransistor) and one modulator for optical input/output. Similarly, an optical memory array consists of an array of electronic memory circuits; each cell in the array has also optical input/output. Within the optical processing array or the optical memory array, local interconnections among neighboring cells can be established electronically. Between the optical processing array and the optical memory array, global interconnections among distant cells can be established optically using the optical input/output in each cell. One important application of such a massively interconnected architecture would be to perform matrix-tensor multiplications (Ref. 1) not only for numeric computing, but also for artificial intelligence and neural computing (Ref. 2). There are three unique aspects associated with the parallel architecture of Figure 1, which may serve to justify this hybrid approach toward optical computing: optical interconnection, 3-D computational topology and optical memory.