Barry M. Pangrle

Splicer: a heuristic approach to connectivity binding

A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.<<ETX>>

On the complexity of connectivity binding

The complexity of the assignment of operations to hardware components to specify the design at a register-transfer level, which is referred to as connectivity binding, is discussed. Connectivity binding is an important issue in high-level behavior synthesis systems that start with abstract behavioral descriptions and synthesize register-transfer level architectures for implementation. The corresponding decision problem is shown to be NP-complete and the complexity of the optimization problem is discussed. This research is intended to provide insight into the nature of this problem. It is shown that problems as simple as performing optimal function unit binding for a hardware structure containing only one commutative operator are hard. >

A grid-based approach for connectivity binding with geometric costs

This paper discusses the problem of connectivity binding with geometric costs and a connectivity binder (GB) built to solve it. The goal of GB is to produce bindings with short interconnection lengths. This is important because routing can account for a significant portion of the layout area and long communication lines tend to lead to longer cycle times due to increased capacitance. Long lines also tend to increase power consumption, so it is important to decrease the interconnection lengths for low-power designs. This issue becomes even more critical as feature sizes are reduced. GB uses a new grid-based connectivity binding approach that incorporates these layout issues into the binding process. The usefulness of this grid-based approach is discussed and demonstrated.

Global mobility based scheduling

The paper addresses the scheduling aspects of the problem of synthesizing control-dominated and processor-like systems from their behavioral descriptions. It is demonstrated that global mobility based scheduling can be used for fast design space exploration, generates schedules comparable to those produced by other global scheduling techniques, and can find operations to be moved into the branch delay slot created by a pipelined controller.<<ETX>>

Generating pipelined datapaths using reduction techniques to shorten critical paths

A new approach to pipelined scheduling is demonstrated. Using a greedy algorithm to generate the initial solution and then applying a series of transformations to the graph is shown to be effective in obtaining optimal and near optimal results without resorting to an exhaustive search. The algorithm handles multicycle pipelined functional units leading to the generation of compact schedules. Using pipelined functional units, the effective throughput is increased and shorter latency times are produced. Thus, in the case of the optimized finite impulse response (FIR) filter, a throughput of three clock cycles, with a latency of nine clock cycles can be obtained using a functional unit specification of five one-cycle adders and three two-cycle pipelined multipliers. In this case the throughput is doubled, and the latency is improved by 33% using pipelined units over non-pipelined units.<<ETX>>

SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system

A new approach is presented for simultaneous scheduling and connectivity binding in a behavioral synthesis system. A branch-and-bound algorithm is applied for scheduling, with connectivity binding performed at each intermediate step. Costs from the connectivity binder are used to direct the search for optimal solutions. This approach allows the program to optimize user defined objectives without any implicit biases, such as trying to achieve the fastest schedule. Some heuristics are presented to estimate the cost of a partially scheduled and bound graph. This helps to prune the search space. The algorithm performance is presented using examples from the literature.<<ETX>>

Conditional and unconditional hardware sharing in pipeline synthesis

This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results.<<ETX>>

GB: A New Grid-Based Binding Approach for High-Level Synthesis

This paper describes a new approach to connectivity binding for high-level synthesis, The new approach is based on deriving geometric communication information from a state graph. The derived information is used to produce bindings that lead to efficient communication structures in the final layouts. It is important because routing may account for a significant portion of the layout area and long communication lines tend to lead to longer machine state cycle times. It becomes even more critical us feature sizes are reduced. The heuristics in this paper use a new grid-based binding approach that produces quulity results on the commonly run benchmarks in only a few tenths of a second of CPU time on a Sun 41490. The work presented in [his paper also has an impact on research in partitioning and in bringing useful information from higher levels of abstraction down to final layout.

Optimization Techniques for Pipelined Scheduling

A new approach is formulated for the synthesis of optimized pipelined data paths. The pipelined data paths are generated by first using a greedy algorithm and then applying a series of moves on the greedy solution to obtain an improved pipelined solution in terms of the number of stages, the number of registers, and the latency time. A set of heuristics is used to reduce the size of the design space explored. Optimization techniques are applied to reduce the height of the datajbw graph. The reduced dataflow graphs are then used to obtain new pipelined solutions. When deciding which pipelined schedule should be generated, the trade-offs between the set of functional units selected and the optimizations that can be performed on the graph with the given functional unit set have to be taken into account. The algorithm has been used successfully in synthesizing pipelined data paths for problems encountered in the current literature. The algorithm has been implemented in C on a MIPS RC3240 RISComputer and hus a typical run time of a few s,econds.

Interconnection synthesis with geometric constraints

The authors describe a simple linear placement model applicable to bit-slice data-paths and to the simultaneous generation of geometric layout with the synthesis of the interconnection nets required for communication. This model allows direct area trade-offs between several alternative interconnection devices such as multiplexers, busses, tri-state drivers and point-to-point wire connections. Addition of geometric constraints to the interconnection synthesis allows accurate interpretation of the designed connections in terms of the actual area required and the relative speed and routing limitations. Use of direct area cost functions in the design of the interconnections leads to different designs than do the a priori cost functions commonly used in high level synthesis systems. The newer designs make better use of the area and routing density than do designs where previously minimized interconnections are mapped into a linear placement. Also described is a new fast heuristic for linear placement which is used interactively as a cost function in the interconnection design.<<ETX>>