Barry Shackleford

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.

FPGA implementation of neighborhood-of-four cellular automata random number generators

Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglias rigorous Diehard suite of random number tests have been discovered. A neighborhood size of four allows a single CA cell to be implemented with a four-input lookup table and a one-bit register which are common building blocks in popular field programmable gate arrays (FPGAs). The investigated networks all had periodic (wrap around) boundary conditions with either 1-d, 2-d, or 3-d interconnection topologies. Trial designs of 64-bit networks using a Xilinx XCV1000-6 FPGA predict a maximum clock rate of 214 MHz to 230 MHz depending upon interconnection topology.

High-performance cellular automata random number generators for embedded probabilistic computing systems

High-performance random number generators (RNGs) can be economically implemented in popular field programmable gate arrays without the need for arithmetic circuitry by employing cellular automata (CA) with a neighborhood size of four and an asymmetrical, non-local neighborhood connection scheme. Each cell (i.e., RNG bit) requires only a single 4-input lookup table and a single flip-flop. From each of various 1-d, 2-d, and 3-d networks with periodic boundary conditions, the 1000 highest entropy CA RNGs were selected from the set of 65,536 possible uniform (all CA truth tables the same) implementations. Each set of 1000 high-entropy CA was then submitted to Marsaglias DIEHARD suite of random number tests. A number of 64-bit, neighbor-of-four CA-based RNGs have been discovered that pass all tests in DIEHARD without resorting to either site spacing or time spacing to improve the RNG quality.

High-performance hardware design and implementation of genetic algorithms

In this chapter, we present a survival-based, steady-state GA designed for efficient implementation in hardware and the design of a pipelined genetic algorithm processor that can generate one new, evaluated chromosome per machine cycle. High performance is obtained by implementing the functions of parent selection, crossover, mutation, evaluation, and survival in hardware in such a manner that each function can be executed in a single machine cycle. When these hardware functions are connected in a linear pipeline (much the same as an assembly line), the net result is the generation a new child chromosome on each machine cycle. The key features of the survival-based, steady-state GA are low selection pressure due to random parent selection, steady-state population maintenance, and replacement of randomly discovered, lesser-fit chromosomes by more-fit offspring. A GA machine prototype is also presented, running at 1 MHz and generating one million new chromosomes per second.