Katsuhiko Seo

A top-down hardware/software co-simulation method for embedded systems based upon a component logical bus architecture

We propose a top-down hardware/software co-simulation method for embedded systems and introduce a component logical bus architecture as an interface between software components and hardware components. Co-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet determined to the stage at which the processor is modeled in register transfer language. A model whose design is based on a component logical bus architecture is replaceable and reusable. By combining such replaceable models, it is possible to quickly realize seamless co-simulation. We further describe experimental results of our approach.

High-performance hardware design and implementation of genetic algorithms

In this chapter, we present a survival-based, steady-state GA designed for efficient implementation in hardware and the design of a pipelined genetic algorithm processor that can generate one new, evaluated chromosome per machine cycle. High performance is obtained by implementing the functions of parent selection, crossover, mutation, evaluation, and survival in hardware in such a manner that each function can be executed in a single machine cycle. When these hardware functions are connected in a linear pipeline (much the same as an assembly line), the net result is the generation a new child chromosome on each machine cycle. The key features of the survival-based, steady-state GA are low selection pressure due to random parent selection, steady-state population maintenance, and replacement of randomly discovered, lesser-fit chromosomes by more-fit offspring. A GA machine prototype is also presented, running at 1 MHz and generating one million new chromosomes per second.

A rapid prototyping method for top-down design of system-on-chip devices using LPGAs

This paper proposes two methods for a rapid prototyping of top-down system-on-chip (SOC) design using laser programmable gate arrays (LPGAs). The first one is a design flow of SOC consisting of four steps: concept-making, virtual-world prototyping, synthesis, and real-world prototyping. The steps can be undertaken individually or in tandem and provisional product models are transformed from upper stream (concept-making) to lower stream (synthesis) either automatically or semi-automatically. This method differs from ordinary rapid prototyping methods in that design evaluation is shifted more upper stream. The SOC device is manufactured early; the steps follow concept-making, virtual-world prototyping, synthesis and real-world prototyping (in the ordinary case, from real-world prototyping to synthesis). This method allows the device to be evaluated in the actual operating environment. The second method we propose is based on LPGAs and use of a real-time production fabrication system (RPFS). With these design methods and environment, we can get a shortest time to market which offers exciting audio and video capabilities while giving designers the flexibility they need to rapidly produce innovative and creative products. This paper describes the application of these methods to develop video signal processors for LCD projectors, demonstrating their efficiency for design tuning and performance optimization.