Bartlomiej Jan Pawlak

On the scalability of source/drain current enhancement in thin film sSOI

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

Experimental studies of dose retention and activation in fin field-effect-transistor-based structures

With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extracting the quantitative active carrier concentration in the fins.With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extr...

The junction challenges in the FinFETs device

The emergence of innovative device architectures such as multiple-gate Field-Effect Transistors (FETs) is a promising solution to scale the CMOS technology beyond the 32 nm. Nevertheless, structures as FinFETs suffer from specific challenges that need to be solved for making these devices competitive for circuits manufacturing. We show, via the use of calibrated analytical model of double-gate transistors, that the reduction of the parasitic resistance is a key enabler for increasing the dynamic performance of the FinFETs device. We demonstrate that the parasitic resistance is mainly dependent on the contact resistance between the Si fin and the Source/Drain (S/D) silicide. But the device behavior depends also on the Source/Drain Extension (SDE) doping profile, which needs to be conformal all along the fin in order to prevent the increase of the spreading resistance between the channel and the SDE. Conformal junctions are also mandatory to avoid pseudo-planar FETs electrical behavior when the SDE junction of the top of the fin is deeper and higher doped than the sidewalls. The case of the standard ion implantation process is studied to highlight the limits of the ion beam implantation to fulfill the doping requirement of the FinFETs technology

Arsenic Junction Thermal Stability and High-Dose Boron-Pocket Activation During SPER in nMOS Transistors

In this letter, thermal stability of arsenic (As) junctions formed by solid-phase epitaxial regrowth and their impact on device performance are investigated. If the temperature does not exceed 800 degC, a 35% junction sheet-resistance improvement over the conventional rapid thermal anneal is observed. The overlap junction resistance is not degraded and transistors, processed exclusively with lowly doped drain junctions, show a significant performance gain. High boron (B)-pocket dose leads to good transistor short-channel effect control, overcoming the B deactivation issue. The impact of B-pocket-related counterdoping and channel-mobility degradation on device characteristics are investigated. In the presence of heavily doped substrates, band-to-band tunneling is the dominant mechanism driving the reverse-bias junction leakage and is higher than the trap-assisted tunneling contribution related to the end-of-range defects

Solid-source doping by using phosphosilicate glass into p-type bulk Si (100) substrate: Role of the capping SiO2 barrier

Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phosphosilicate glass was split to understand the role of the SiO2 capping layer in detail for scaled devices. 3-nm SiO2 cap could not prevent out-diffusion during the drive-in annealing, and it showed much higher sheet resistance and lower retained phosphorus dose in the Si substrate. The highest retained phosphorus dose in the Si substrate was observed for 6-nm SiO2 cap and resulted in 1.8 × 1014 atoms/cm2 retained phosphorus dose with 96% activation level after 1050 °C 4 s rapid thermal annealing. Thicker SiO2 caps than 6 nm were not beneficial since 10-nm SiO2 cap showed a higher sheet resistance value as well as lower phosphorus activation level (82%) compared to 6-nm SiO2 cap even though both the process conditions showed same phosphorus profiles after the drive-in annealing. That sheet resistance increase with 10-nm SiO2 cap could be caused by heterogeneous surface formation on the Si substrate with a prolonged SiO2 atomic layer deposition process.Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phospho...

Characteristics and Integration Challenges of FinFET-based Devices for (Sub-)22nm Technology Nodes Circuit Applications

for (Sub-)22nm Technology Nodes Circuit Applications A. Veloso, M. J. H. van Dal, N. Collaert, A. De Keersgieter, L. Witters, R. Rooyackers, A. Redolfi, S. Brus, R. Duffy, B. J. Pawlak, G. Vellianitis, B. Duriez, T. Mérelle, P. P. Absil, S. Biesemans, M. Jurczak, T. Hoffmann, and R. J. P. Lander IMEC, NXP-TSMC Research Center, Kapeldreef 75, B-3001 Leuven, Belgium Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be