Baruch Feldman

Simulation of junctionless Si nanowire transistors with 3 nm gate length

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼1 nm wire diameter and ∼3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowirebased devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼1 nm wire diameter and ∼3 nm gate length, and that the junctionless transistor [1, 2] may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.

Calculation of Cu/Ta interface electron transmission and effect on conductivity in nanoscale interconnect technology

Resistivity augmentation in nanoscale metal interconnects is a performance limiting factor in integrated circuits. Here we present calculations of electron scattering and transmission at the interface between Cu interconnects and their barrier layers, in this case Ta. We also present a semiclassical model to predict the technological impact of this scattering and find that a barrier layer can significantly decrease conductivity, consistent with previously published measurements.

New regions for a chameleon to hide

We show that inclusion of an extremely small quartic coupling constant in the potential for a nearly massless scalar field greatly increases the experimentally allowed region for the mass term and the coupling of the field to matter.

Dependence of resistivity on surface profile in nanoscale metal films and wires

We extend quantum models of nanowire surface scattering to incorporate bulk resistivity and extract an expression for the increased resistivity due to surface roughness. To learn how to improve conductivity, we calculate conductivity degradation from individual wavelengths of surface roughness, and show how these can be convolved to give resistivity for arbitrary surfaces. We review measurements from Cu films and conclude that roughness at short wavelengths (less than 100 nm) dominates scattering, and that primarily specular scattering should be achievable for root-mean-square roughness below about 0.7 nm.

Transport properties and electrical device characteristics with the TiMeS computational platform: Application in silicon nanowires

Nanoelectronics requires the development of a priori technology evaluation for materials and device design that takes into account quantum physical effects and the explicit chemical nature at the atomic scale. Here, we present a cross-platform quantum transport computation tool. Using first-principles electronic structure, it allows for flexible and efficient calculations of materials transport properties and realistic device simulations to extract current-voltage and transfer characteristics. We apply this computational method to the calculation of the mean free path in silicon nanowires with dopant and surface oxygen impurities. The dependence of transport on basis set is established, with the optimized double zeta polarized basis giving a reasonable compromise between converged results and efficiency. The current-voltage characteristics of ultrascaled (3 nm length) nanowire-based transistors with p-i-p and p-n-p doping profiles are also investigated. It is found that charge self-consistency affects the device characteristics more significantly than the choice of the basis set. These devices yield source-drain tunneling currents in the range of 0.5 nA (p-n-p junction) to 2 nA (p-i-p junction), implying that junctioned transistor designs at these length scales would likely fail to keep carriers out of the channel in the off-state.

First Principle-Based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors

Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction, and thus, can be easier to implement in aggressive geometries. In this paper, we explore a similar architecture for aggressively scaled devices with the channel consisting of doped carbon nanotubes (CNTs). Gate all around field effect transistor (FET) structures are investigated for n- and p- type doping. Current-voltage characteristics and subthreshold characteristics for a CNT-based junctionless FET is compared with a junctionless silicon nanowire FET with comparable dimensions. Despite the higher on-current of the CNT channels, the device characteristics are poorer compared to the silicon devices due to the smaller CNT bandgap.

Atomic scale simulation of a junctionless silicon nanowire transistor

We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.

Understanding limits to conductivity of metal nanowires

Reduced conductivity in sub-100nm metal wires used as interconnects is a performance limiting factor in integrated circuits. In order to understand the sources of conductivity degradation with the aim of optimizing metal nanowire conductivity, we have analyzed potential sources of electron momentum loss, including surface roughness scattering, grain boundary reflection and interactions with Ta liner layers. Based on the roughness spectrum of metal films, we conclude that primarily specular scattering should be achievable at metal/dielectric interfaces for Cu technology. Using non-equilibrium Greens function methods, we find substantial reflection at Cu and Ag grain boundaries and find that both the change in grain orientation and disorder in the boundary contribute significantly to reflectivity. Using the same approach for Cu/Ta interfaces, we predict substantial conductivity degradation due to electron interactions with thin liner layers. Based on our analyses, we conclude by suggesting promising directions for maximizing conductivity as interconnect dimensions shrink further below 100nm.