Basel Halak

Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels

An on-chip intermodule self-timed communication system is considered in which symbols are encoded by means of phase difference between transitions of signals on parallel wires. The reliability of such a channel is governed and significantly lowered by capacitive crosstalk effects between adjacent wires. A more robust high-speed phase-encoded channel can be designed by minimizing its vulnerability to crosstalk noise. This paper investigates the impact of crosstalk on phase-encoded transmission channels. A functional fault model is presented to characterize the problem. Two fault-tolerant schemes are introduced which are based on information redundancy techniques and a partial-order coding concept. The area overheads, performance, and fault-tolerant capability of those methods are compared. It is shown that a substantial improvement in the performance can be obtained for four-wire channels when using the fault-tolerant design approach, at the expense of 25 percent of information capacity per symbol.

Power balanced circuits for leakage-power-attacks resilient design

The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. This work evaluates the security of cryptographic circuits designed with this technology against the newly developed LPA. Two forms of LPA are investigated, one is based on differential power analysis (LDPA) and the other based on Hamming weight analysis (LHPA). Simulations performed at 90nm CMOS technology reveal that (m-of-n) circuits are totally resilient to LHPA and have a higher security level against LDPA than standard logic circuits.

The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk

With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability.

TCO-PUF: A subthreshold physical unclonable function

A Physical Unclonable Function (PUF) is a promising technology towards comprehensive security protection for integrated circuit applications. It provides a secure method of hardware identification and authentication by exploiting inherent manufacturing process variations to generate a unique response for each device. Subthreshold Current Array PUFs, which are based on the non-linearity of currents and voltages in MOSFETs in the subthreshold region, provide higher security against machine learning-based attacks compared with delay-based PUFs. However, their implementation is not practical due to the low output voltages generated from transistor arrays. In this paper, a novel architecture for a PUF, called the “Two Chooses One” PUF or TCO-PUF, is proposed to improve the output voltage ranges. The proposed PUF shows excellent quality metrics. The average inter-chip Hamming distance is 50.23%. The reliability over the temperature and ±10% supply voltage fluctuations is 91.58%. In terms of security, on average TCO-PUF shows higher security compared to delay-based PUFs and existing designs of Subthreshold Current Array PUFs against machine learning attacks.

NBTI aging evaluation of PUF-based differential architectures

Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.

Overview of PUF-based hardware security solutions for the internet of things

The Internet of Things (IoT) consists of numerous inter-connected resource-constrained devices such as sensors nodes and actuators, which are linked to the Internet. By 2020 it is anticipated that the IoT paradigm will include approximately 20 billion connected devices. The interconnection of such devices provides the ability to collect a huge amount of data for processing and analysis. A significant portion of the transacted data between IoT devices is private information, which must not in any way be eavesdropped on or tampered with. Security in IoT devices is therefore of paramount importance for further development of the technology. Such devices typically have limited area and energy resources, which makes the use of classic cryptography prohibitively expensive. Physically Unclonable Functions (PUFs) are a class of novel hardware security primitives that promise a paradigm shift in many security applications; their relatively simple architecture can answer many of the security challenges of energy-constrained IoT devices. In this paper, we discuss the design challenges of secure IoT systems; then we explain the principles of PUFs; finally we discuss the outstanding reliability and security problems of PUF technology and outline the open research questions in this field.

Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation

Modern interconnect performance is greatly affected by crosstalk noise because of continuous decrease in wire separation and increase in its aspect ratio with technology scaling. Such noise is highly dependent on data transition patterns, coding techniques have been proposed to alleviate crosstalk delay by controlling these patterns. The complexity of available crosstalk avoidance codes, along with their associated overheads, increase rapidly with bus width. The lack of energy and area-efficient method to implement such codes has so far prevented their use in practical designs. This study presents a generic framework, which allows efficient implementations of crosstalk avoidance codes; the essence of the proposed approach is based on the partial coding concept. Quantitative analysis performed in 32 nm technology shows that substantial savings in area and energy costs can be obtained using the proposed technique compared with both existing coding solutions and conventional methods as shielding and repeater insertion.

Statistical analysis of crosstalk-induced errors for on-chip interconnects

The impact of crosstalk noise on the resilience of on-chip communication links in the presence of parametric variations is investigated. A novel metric called crosstalk error rate is developed which can be a valuable tool for designers to predict the crosstalk effects and explore interconnect design techniques in order to achieve the target performance with minimum overheads. Closed-form expressions of crosstalk error rate are presented. This metric is used to compare different crosstalk avoidance methods in the 90 nm technology.

Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods

The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel buses under different latency and power constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90-nm technology.

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques.