Mark Zwolinski

Mutual information theory for adaptive mixture models

Many pattern recognition systems need to estimate an underlying probability density function (pdf). Mixture models are commonly used for this purpose in which an underlying pdf is estimated by a finite mixing of distributions. The basic computational element of a density mixture model is a component with a nonlinear mapping function, which takes part in mixing. Selecting an optimal set of components for mixture models is important to ensure an efficient and accurate estimate of an underlying pdf. Previous work has commonly estimated an underlying pdf based on the information contained in patterns. In this paper, mutual information theory is employed to measure whether two components are statistically dependent. If a component has small mutual information, it is statistically independent of the other components. Hence, that component makes a significant contribution to the system pdf and should not be removed. However, if a particular component has large mutual information, it is unlikely to be statistically independent of the other components and may be removed without significant damage to the estimated pdf. Continuing to remove components with large and positive mutual information will give a density mixture model with an optimal structure, which is very close to the true pdf.

Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification

The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.

Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure

Differential power analysis (DPA) attack is a major concern for secure embedded devices (Ravi et al., 2004)-(Ors et al., 2004). Currently proposed countermeasures (Pramstaller, 2005)-(Tin and Verbauwhede, 2004) to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, random dynamic voltage and frequency scaling (RDVFS) has been proposed (Yang et al., 2005) as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, the authors show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. The authors propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data

Reversible Logic to Cryptographic Hardware: A New Paradigm

Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and five-to-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks.

Analogue electronic circuit diagnosis based on ANNs

Feed-forward artificial neural networks (ANNs) have been applied to the diagnosis of nonlinear dynamic analogue electronic circuits. Using the simulation-before-test (SBT) approach, a fault dictionary was first created containing responses observed at all inputs and outputs of the circuit. The ANN was considered as an approximation algorithm to capture mapping enclosed within the fault dictionary and, in addition, as an algorithm for searching the fault dictionary in the diagnostic phase. In the example given DC and small signal frequency domain measurements were taken as these data are usually given in device’s data-sheets. A reduced set of data per fault (DC output values, the nominal gain and the 3 dB cut-off frequency, measured at one output terminal) was recorded. Soft (parametric) and catastrophic (shorts and opens) defects were introduced and diagnosed simultaneously and successfully. Large representative set of faults was considered, i.e., all possible catastrophic transistor faults and qualified representatives of soft transistor faults were diagnosed in an integrated circuit. The generalization property of the ANNs was exploited to handle noisy measurement signals.

Generation and verification of tests for analogue circuits subject to process parameter deviations

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of dynamic voltage scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.

Divided Backend Duplication Methodology for Balanced Dual Rail Routing

Dual Rail Precharge circuits offer an effective way to address Differential Power Analysis Attacks, provided routing of differential signals is fully balanced. Fat Wire [1] and Backend Duplication [2] methods address this problem. However they do not consider the effect of coupling capacitance on adjacent differential signals. In this paper we propose a new method, Divided Backend Duplication, which is based on Divided Wave Dynamic Differential Logic [3] and Backend Duplication [2], that effectively addresses balanced routing problem of Dual Rail Precharge circuits. Experimental results on an AES test circuit in 130nm technology show improvements in achieving a balanced dual rail design. Further our method can also be successfully applied to FPGAs. Results from an sbox test circuit implementation on a Xilinx FPGA are presented.

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.