S. Saqib Khursheed

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs

Three-dimensional Integrated Circuits (3D-ICs) vertically stack multiple silicon dies to reduce overall wire length, power consumption, and allow integration of heterogeneous technologies. Through-silicon-vias (TSVs) which act as vertical links between layers pose challenges for 3D integration design. TSV defects can happen in fabrication process and bonding stage, which can reduce the yield and increase the cost. Recent work proposed the employment of redundant TSVs to improve the yield of 3D-ICs. This paper presents a redundant TSVs grouping technique, which partitions regular and redundant TSVs into groups. For each group, a set of multiplexers are used to select good signal paths away from defective TSVs. We investigate the impact of grouping ratio (regular-to-redundant TSVs in one group) on trade-off between yield and hardware overhead. We also show probabilistic models for yield analysis under the influence of independent and clustering defect distributions. Simulation results show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratios lead to achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios.

Bridging Fault Test Method With Adaptive Power Management Awareness

A key design constraint of circuits used in hand-held devices is the power consumption, mainly due to battery-life limitations. Adaptive power management (APM) techniques aim at increasing the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi- automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits.

Process Variation-Aware Test for Resistive Bridges

This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesized International Symposium on Circuits and Systems benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

Diagnosis of Multiple-Voltage Design With Bridge Defect

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

Improved DFT for Testing Power Switches

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.

Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software, respectively. To validate the methodology, ARM® Cortex™-M0 embedded microprocessor (provided by our industrial project partner) is implemented in field-programmable gate array and further synthesized using 65-nm technology to quantify the cost in terms of area, latency, and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multibit errors for a wide range of fault rates.

Resistive Bridging Faults DFT with Adaptive Power Management Awareness

A key design constraint of circuits used in handheld devices is the power consumption, due mainly to the limitations of battery life. The employment of adaptive power management (APM) methods optimizes the power consumption of such circuits. This paper describes an effective APM-aware DFT technique that consists of a Test Generation Suite, including fault list generation, test pattern generation and fault simulation. The test generation suite is capable of generating test patterns for multiple supply voltage (Vdd) settings to maximize coverage of resistive bridging faults; and a method to reduce the number of Vdd settings without compromising the fault coverage in order to reduce the cost of test. Preliminarily validations of the proposed DFT technique using a number of benchmark circuits demonstrate its effectiveness.

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present, there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using the BSIM4 transistor model. To speed up the computation time and without compromising simulation accuracy (achieved through BSIM4), two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65 nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.

Delay Test for Diagnosis of Power Switches

Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The proposed diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations.

Modeling the impact of process variation on resistive bridge defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.