Bassam Shaer

Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits

This brief introduces a partitioning algorithm, which facilitates pseudoexhaustive testing, to detect and locate faults in digital VLSI circuits. The algorithm is based on an analysis of circuits primary input cones and fanout (PIFAN) values. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous ISCAS 1985 and 1989 benchmark circuits containing up to 5597 gates. Our results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms.

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuits primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced.

Partitioning algorithm to enhance VLSI testability

In this paper we introduce a new partitioning algorithm which facilitates pseudo-exhaustive testing of combinational circuits. This algorithm is based on an analysis of a circuit’s Primary Input cones and FANout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. Feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 3,512 gates. Our results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms. In addition, our algorithm is based upon pseudo-exhaustive testing methods and fault simulation is not required for test pattern generation and grading; hence, engineering design time and cost are further reduced.

Testable sequential circuit design: partitioning for pseudoexhaustive test

In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work.

Pseudo-exhaustive testing of sequential circuits

A new sequential circuit partitioning algorithm is introduced which enhances pseudo-exhaustive testing. Our PIFAN algorithm is based on an analysis of Primary Input cones and FANout values. Results are presented which show that PIFAN offers significant reductions in hardware overhead and test time when compared to alternative partitioning algorithms.

New methods for computing the Pisarenko vector

In this paper we show that the Pisarenko vector for harmonic retrieval problems can be obtained without explicit eigendecomposition: The smallest eigenvalue and corresponding eigenvector of a covariance matrix are computed using higher order convergent methods which include the Newton method as special case. An implementation that relies on QR factorization and less on matrix inversion is presented. This approach can also be used to compute the largest eigenpair by appropriately choosing the initial condition. Additionally, an approach is proposed to accelerate the developed methods considerably by using the double step Newton method. Several randomly generated test problems are used to evaluate the performance and the computational cost of the methods.