Sami A. Al-Arian

A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs

Todays built-in current sensor (BICS) techniques provide I/sub DDQ/ current sensitivity which is adequate for testing and diagnosing near-micron CMOS ICs. However, faulty and fault-free I/sub DDQ/ can become indiscernible at deep submicron levels. This paper describes a novel BICS methodology which improves fault detectability and diagnosability in ULSI CMOS ICs.

A new heuristic algorithm for estimating signal and detection probabilities

The problem of computing signal probabilities of digital circuits arises in the context of random testing, pseudorandom testing, and testability analysis. This paper presents a simple but effective algorithm for estimating signal probabilities, which provides significantly better estimates of signal probabilities than the weighted averaging algorithm and most importantly is linear in the product of circuit size and the number of primary inputs. Based on this algorithm, the detection probabilities of stuck-at faults are estimated. Experimental results using ISCAS benchmark circuits show the effectiveness and the improvement of this technique over the simple algorithm as well as the weight averaging algorithm. The correlation coefficients of the results are extremely good and the algorithm is very fast.

Improving the testability of VLSI circuits through partitioning

The field of test engineering for very large scale integrated (VLSI) circuits is inundated with requirements to improve test coverage, reduce overhead and decrease development time. In response to this is a design methodology that will eliminate the test generation effort. This will reduce overall production costs, and provide a savings for products manufactured in low volumes. The approach utilizes known methods of partitioning circuits into smaller portions. Each portion being fully testable, the entire circuit is fully testable, neglecting portions of the Built-In-Self-Test (BIST) circuit itself. Overall, the results show that for small volume production, this methodology could be the best available option for a large class of circuits. Furthermore, it also provides a high degree of reliability in terms of the quality of the manufacturing test, and does not require expensive test devices, such as high-speed wafer-probe testers. The new design cycle that is presented eliminates time for test generation in lieu of approximately fifteen-percent impact in performance and size.<<ETX>>

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuits primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced.

A method for consistent fault coverage reporting

Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage.<<ETX>>

Wafer scale architecture for an FFT processor

A description is given of research on a WSI FFT processor. Attention is focused on the design methodology, architecture, and sparing strategy and restructuring. The basic cells utilized are the MSA and the coefficient ROM. The wafer thus has only two types of cell, making the algorithm highly suitable for restructable wafer-scale integration (WSI) design. The restructuring algorithm is discussed briefly, and the tradeoffs between cell redundancy, wafer-area utilization, and effective yield are evaluated. Indeed, interest in WSI arises from expectations of higher speed, better reliability, and significant improvement in the circuit density. This FFT wafer represents the first of several envisioned in large-scale signal processing and computing under a DARPA microelectronics project in progress.<<ETX>>

Defining a standard for fault simulator evaluation

An acceptable standard is developed for relating fault simulator results from different simulators. Each simulator should verify the good circuit and evaluate the effectiveness of the generated test patterns (fault coverage). A hypothetical standard set of characteristics are proposed and each of the simulators are redefined in terms of the standard. These recommendations for evaluating these fault simulators and relating them to the standard include: the use of the same circuit topology (structure) and same ordered test vectors. However, the use of fault classes as a basis for evaluating the fault coverage is the major result of this effort.<<ETX>>

Partitioning algorithm to enhance VLSI testability

In this paper we introduce a new partitioning algorithm which facilitates pseudo-exhaustive testing of combinational circuits. This algorithm is based on an analysis of a circuit’s Primary Input cones and FANout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. Feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 3,512 gates. Our results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms. In addition, our algorithm is based upon pseudo-exhaustive testing methods and fault simulation is not required for test pattern generation and grading; hence, engineering design time and cost are further reduced.

Pseudo-exhaustive testing of sequential circuits

A new sequential circuit partitioning algorithm is introduced which enhances pseudo-exhaustive testing. Our PIFAN algorithm is based on an analysis of Primary Input cones and FANout values. Results are presented which show that PIFAN offers significant reductions in hardware overhead and test time when compared to alternative partitioning algorithms.

A statistical methodology for modeling and analysis of path delay faults in VLSI circuits

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has dramatically increased. Testing such circuits is becoming a severe problem. With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits which result from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test (Shelly, J. H. and Trayon, D. R., Statistical techniques of timing verification. In Proc. 20th Design Automation Conf., 1983, pp. 396–402; Tendokar, N. N., Analysis of timing failures due to random AC defects in VLSI circuits. In Proc. 22nd Design Automation Conf., 1985, pp. 709–714; Park, E. S., Mercer, M. R. and Williams, T. W., A statistical model for delay fault testing. IEEE Design and Test of Computers, 1989, February, 45–55). In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits (Hamad, M. and Landis, D., A statistical model for path delay faults in VLSI circuits. In Proc. IEEE South East Conf., April 1996, pp. 388–392) which takes into account multiple delay faults along any signal path. We define and compute the path delay fault probabilities for all paths in a circuit; the single fault assumption is only a special case of our path delay fault model. Furthermore, we demonstrate how our statistical model is used to predict such important information as the maximum number of path delay faults in a circuit. Finally, we show that when multiple faults are considered during circuit analysis, the path delay fault probability, pp, and not the delay defect probability, p, should be used in the evaluation of system parameters such as statistical delay fault coverage, yield, and AC quality level.