Bassam Tabbara

Cycle and phase accurate DSP modeling and integration for HW/SW co-verification

We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with other hardware and software components. A common approach to the modeling of processors for HW/SW co-verification relies on instruction-accurate ISA models combined (i.e. wrapped) with the bus interface model (BIM) that generate the clock/phase-accurate timing at the components interface pins. However, for DSPs and new microprocessors with complex architectural features this approach is from our perspective not acceptable. The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them. We therefore propose an alternative approach in which the processor ISAs themselves are modeled in a full cycle/phase-accurate fashion. The bus interface model is then reduced to just modeling the connection to the pins. Our models have been integrated into a number of cycle-based and event-driven system simulation environments. We present one such experience in incorporating these models into a VHDL environment. The accuracy has been verified cycle-by-cycle against the gate/RTL level models. Multiprocessor debugging and observability into the precise cycle-accurate processor state is provided. The use of co-verification models in place of the RTL resulted in system speedups up to 10 times, with the cycle-accurate ISA models themselves reaching performances of up to 123 K cycles/s.

Advanced techniques for RTL debugging

Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a designs multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.

Fast hardware-software co-simulation using VHDL models

We describe a technique for hardware-software co-simulation that is almost cycle-accurate, and does nor require the use of interprocess communication for a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from basic block-level timing estimates. Hardware is also modeled in VHDL, and can be either pre-existing intellectual property or synthesized to RTL from a functional specification. Execution of the VHDL processes modeling software tasks is coordinated by a process emulating the target RTOS behavior. The effects of changing the hardware/software partition can be quickly estimated by changing a process parameter defining its target implementation and the processor on which it is running.

Models and Representations

This chapter describes the models and specification methods that are used inside the POLIS system, both to specify the complete system, and to perform analysis, synthesis, and optimization. It also contains a brief review of related models reported in the literature.

Integration of retiming with architectural floorplanning

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-offs and delay constraints are considered. The main result is that the concavity of the trade-off function allows for casting this problem into a classical minimum area retiming problem. The solution paves the way for retiming to be incorporated in the architectural floorplanning stage of a design flow tailored for deep sub-micron circuits. Some examples and a register-based interconnect strategy suitable to the developed retiming technique on global wires is presented.

Task response time optimization using cost-based operation motion

We present a technique for task response time improvement based on the concept of code motion from the software domain. Relaxed Operation Motion (ROM) is a simple yet powerful approach for performing safe and useful operation motion from heavily executed portions of a design task to less visited segments. We introduce here our algorithm, how it differs from other code motion approaches, and its application to the embedded systems domain. Results of our investigation indicate that cost-guided operation motion has the potential to improve task response time significantly.

Conclusions and Future Research Opportunities

We have presented our work on function / architecture optimization and co-design of embedded systems; a methodology that applies to both hardware and software synthesis for ASIC and ASIP targets, as well as for programmable platforms. With increasing market pressures including shrinking time to market and rising cost of layout masks, the importance of the latter architectural target cannot be over-emphasized. Figure 10.1 displays the envisioned required paradigm for programmable platforms1 and how function / architecture co-design comes into the picture. The Figure is intended to show that we typically have an incompletely specified, possibly “vague” (non-deterministic if you wish) functional specification captured by the trapezoid. Similarly for the architecture we use an inverted trapezoid to emphasize that several possible alternative architectures (parameterizations of a platform if you wish) may be suitable for realizing our intent. The specification casts a shadow on the architectural space in the refinement levels on how it can be realized. In turn the application architectural specification space sheds a light on what can be realized with the architecture as required by the application. The architecture can be more powerful than what the typically restricted functional specification can describe; in fact this is most often the case in architectures with large memories and ways to access these memories (essentially Turing Complete), where the architecture is definitely more powerful than what we would like to describe (or even can in a restricted language) at the functional level.

Hardware/Software Co-Synthesis and Estimation

Our proposed overall co-synthesis flow is shown in Figure 7.1. The CDFG is built after performing the FFG task representation architecture independent optimizations, as well as the architecture dependent AFFG optimizations, followed by the optimal mapping step. After the AFFG is mapped onto an optimized CDFG we proceed with reactive synthesis. In the next section, we describe the CDFG representation, and the hardware and software co-synthesis techniques of the Polis co-design tool. A design environment based on hardware / software co-synthesis allows the designer to specify the system in a high level formal language (e.g. Esterel [16] front-end that our flow uses) by describing the functionality of each block and how blocks are connected together.

Function / Architecture Optimization and Co-Design Flow

In the previous Chapters, we layed the foundation for the formal function / architecture optimization and co-design methodology. We presented a suitable abstract representation on which function / architecture trade-off is performed through refinement of the function, and abstraction of the architecture in Chapter 3. We then focused on discussing optimization of both control and data and how we introduced it into the co-design process as a crucial player in the analysis and redundancy removal of the information embodied in the function as it is constrained by the application and architecture demands. We overviewed architecture-independent optimizations in Chapter 4, architecture / function trade-offs in Chapter 5, and then mapping of the function onto the architecture in Chapter 6. Integration with synthesis was presented in Chapter 7.

System Level Design of Embedded Systems

Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators [5]. In today’s world there is a wide proliferation of such electronic devices in everything from tea kettles to life-critical systems. Up till very recently, embedded systems have been designed in an ad hoc fashion based on manual interference and guidance. With increasing complexity, formal methodologies that incorporate HW/SW trade-off analysis and evaluation, and validation at the highest possible abstraction level have become essential. Obviously, an overhead is incurred in this top-down process: quality of the final output is typically tradedoff with increased productivity, but as we will show, this overhead can be again managed and put within bounds if the methodology includes constraint-driven optimizations; the subject of the upcoming Chapters.