Abdallah Tabbara

Design and specification of embedded systems in Java using successive, formal refinement

Successive, formal refinement is a new approach for specification of embedded systems using a general-purpose programming language. Systems are formally modeled as abstractable synchronous reactive systems, and Java is used as the design input language. A policy of use is applied to Java, in the form of language usage restrictions and class-library extensions to ensure consistency with the formal model. A process of incremental, user-guided program transformation is used to refine a Java program until it is consistent with the policy of use. The final product is a system specification possessing the properties of the formal model, including deterministic behavior, bounded memory usage and bounded execution time. This approach allows systems design to begin with the flexibility of a general-purpose language, followed by gradual refinement into a more restricted form necessary for specification.

A force-directed maze router

A new routing algorithm is presented. It is based on a multiple star net model, force-directed placement and maze searching techniques. The algorithm inherits the power of maze routing in that it is able to route complex layouts with various obstructions. The large memory requirement of the conventional maze algorithm is alleviated through successive net refinement, which constrains the maze searching to small regions. The algorithm shows advantages in routing designs with complicated layout obstructions.

A timing-driven macro-cell placement algorithm

The timing-driven macro-cell placement algorithm described is based on the force-directed technique. The proposed star net model enables more accurate timing analysis, hence path delay constraints can be handled. In addition, the placer provides functions such as determination of cell orientation, routing estimation and pad placement. The algorithm is iterative and incremental, allowing flexibility in the physical design flow. The placer competes with commercial physical design tools and gives better results in terms of path delay.

Retiming for DSM with area-delay trade-offs and delay constraints

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe [1991]. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work we show how this approach can be reapplied in the DSM domain when area-delay trade-offs and delay constraints are considered. The main result is that the concavity of the tradeoff function allows for a casting of this DSM problem into a classical minimum area retiming problem whose solution is polynomial time solvable.

Integration of retiming with architectural floorplanning

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-offs and delay constraints are considered. The main result is that the concavity of the trade-off function allows for casting this problem into a classical minimum area retiming problem. The solution paves the way for retiming to be incorporated in the architectural floorplanning stage of a design flow tailored for deep sub-micron circuits. Some examples and a register-based interconnect strategy suitable to the developed retiming technique on global wires is presented.

The JavaTime approach to mixed hardware-software system design

We describe an approach for using Java as a basis for a design and specification language for embedded systems and use our JavaTime system to illustrate many aspects of the approach. Java is a pragmatic choice for several reasons. Since it is a member of the C “family” of languages, it is familiar to designers. Unlike C and C++, it has standard support for concurrency. Its treatment of arrays permits better static and dynamic error checking than is conveniently feasible in C and C++. Finally, while Java’s expressive power is comparable to C++, it is a much simpler language, that greatly eases the task of introducing additional analysis into compilers.

Task response time optimization using cost-based operation motion

We present a technique for task response time improvement based on the concept of code motion from the software domain. Relaxed Operation Motion (ROM) is a simple yet powerful approach for performing safe and useful operation motion from heavily executed portions of a design task to less visited segments. We introduce here our algorithm, how it differs from other code motion approaches, and its application to the embedded systems domain. Results of our investigation indicate that cost-guided operation motion has the potential to improve task response time significantly.

Conclusions and Future Research Opportunities

We have presented our work on function / architecture optimization and co-design of embedded systems; a methodology that applies to both hardware and software synthesis for ASIC and ASIP targets, as well as for programmable platforms. With increasing market pressures including shrinking time to market and rising cost of layout masks, the importance of the latter architectural target cannot be over-emphasized. Figure 10.1 displays the envisioned required paradigm for programmable platforms1 and how function / architecture co-design comes into the picture. The Figure is intended to show that we typically have an incompletely specified, possibly “vague” (non-deterministic if you wish) functional specification captured by the trapezoid. Similarly for the architecture we use an inverted trapezoid to emphasize that several possible alternative architectures (parameterizations of a platform if you wish) may be suitable for realizing our intent. The specification casts a shadow on the architectural space in the refinement levels on how it can be realized. In turn the application architectural specification space sheds a light on what can be realized with the architecture as required by the application. The architecture can be more powerful than what the typically restricted functional specification can describe; in fact this is most often the case in architectures with large memories and ways to access these memories (essentially Turing Complete), where the architecture is definitely more powerful than what we would like to describe (or even can in a restricted language) at the functional level.

Hardware/Software Co-Synthesis and Estimation

Our proposed overall co-synthesis flow is shown in Figure 7.1. The CDFG is built after performing the FFG task representation architecture independent optimizations, as well as the architecture dependent AFFG optimizations, followed by the optimal mapping step. After the AFFG is mapped onto an optimized CDFG we proceed with reactive synthesis. In the next section, we describe the CDFG representation, and the hardware and software co-synthesis techniques of the Polis co-design tool. A design environment based on hardware / software co-synthesis allows the designer to specify the system in a high level formal language (e.g. Esterel [16] front-end that our flow uses) by describing the functionality of each block and how blocks are connected together.

Function / Architecture Optimization and Co-Design Flow

In the previous Chapters, we layed the foundation for the formal function / architecture optimization and co-design methodology. We presented a suitable abstract representation on which function / architecture trade-off is performed through refinement of the function, and abstraction of the architecture in Chapter 3. We then focused on discussing optimization of both control and data and how we introduced it into the co-design process as a crucial player in the analysis and redundancy removal of the information embodied in the function as it is constrained by the application and architecture demands. We overviewed architecture-independent optimizations in Chapter 4, architecture / function trade-offs in Chapter 5, and then mapping of the function onto the architecture in Chapter 6. Integration with synthesis was presented in Chapter 7.